Intel E3845 FH8065301487715 Ficha De Dados
Códigos do produto
FH8065301487715
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
283
12.3.2
DTR0—Offset 1h
DRAM Timing Register 0
Access Method
Default: 43001110h
16
0h
RW/P/L
DIMMFLIP:
DIMM Flip Required. BIOS must set this bit to 1 if the total size of DIMM1 is
greater than the total size of DIMM0. DIMM Flipping simplifies rank decoding in dual-
DIMM configuration when the DIMMs are not equal in size by mapping the low addresses
to the larger DIMM.
15
0h
RO
Rsvd_15_DRP:
Reserved
14
0h
RW/P/L
RSIEN:
Rank Select Interleave Enable. 0 - Rank Select Interleave Disabled 1 - Rank
Select Interleave Enabled Note: Rank select interleave enable should be set the same
for both the Dunit and Bunit.
13
0h
RO
Rsvd_13_DRP:
Reserved
12:11
0h
RW/P/L
DIMMDDEN1:
DIMM 1 Device Density. This sets the density of the DRAM devices
populated in DIMM 1 (Rank 0 and Rank 1). 00 - 1Gbit 01 - 2Gbit 10 - 4Gbit 11 - 8Gbit
10:9
0h
RW/P/L
DIMMDWID1:
DIMM 1 Device Width. Indicates the width of the DRAM devices
populated in DIMM 1 (Rank 0 and Rank 1). 00 - x8 01 - x16 10 - x32 11 - Reserved
8
0h
RO
Rsvd_8_DRP:
Reserved
7:6
0h
RW/P/L
DIMMDDEN0:
DIMM 0 Device Density. This sets the density of the DRAM devices
populated in DIMM 0 (Rank 0 and Rank 1). 00 - 1Gbit 01 - 2Gbit 10 - 4Gbit 11 - 8Gbit
5:4
0h
RW/P/L
DIMMDWID0:
DIMM 0 Device Width. Indicates the width of the DRAM devices
populated in DIMM 0 (Rank 0 and Rank 1). 00 - x8 01 - x16 10 - x32 11 - Reserved
3
0h
RW/P/L
RKEN3:
DIMM 1, Rank 1 Enabled. Should be set to 1 when DIMM1 is populated and has
2 ranks to enable the use of this rank. Otherwise, must be set to 0.
2
0h
RW/P/L
RKEN2:
DIMM 1, Rank 0 Enabled. Should be set to 1 when DIMM1 is populated to
enable the use of this rank. Otherwise, must be set to 0.
1
0h
RW/P/L
RKEN1:
DIMM 0, Rank 1 Enabled. Should be set to 1 when DIMM0 is populated and has
2 ranks to enable the use of this rank. Otherwise, must be set to 0.
0
0h
RW/P/L
RKEN0:
DIMM 0, Rank 0 Enabled. Should be set to 1 when DIMM0 is populated to
enable the use of this rank. Otherwise, must be set to 0.
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Message Bus Register
(Size: 32 bits)
Offset:
Op Codes:
h - Read, h - Write
h - Read, h - Write