Intel E3815 FH8065301567411 Ficha De Dados
Códigos do produto
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4427
bits (bits 0, 1, 3) can get set after a reset if their respective modem signals are active
(see individual bits for details), a read of the MSR after reset can be performed to
prevent unwanted interrupts.
Access Method
Default: 00h
Type:
I/O Register
(Size: 8 bits)
7
4
0
0
0
0
0
0
0
0
0
DC
D
RI
DS
R
CTS
DDC
D
TE
RI
DD
SR
DC
T
S
Bit
Range
Default &
Access
Description
7
0b
RO
Data Carrier Detect (DCD):
This is used to indicate the current state of the modem
control line dcd_n. This bit is the complement of dcd_n. When the Data Carrier Detect
input (dcd_n) is asserted it is an indication that the carrier has been detected by the
modem or data set. '0' - dcd_n input is de-asserted (logic 1) '1' - dcd_n input is
asserted (logic 0) In Loopback Mode (MCR[4] set to one), DCD is the same as MCR[3]
(Out2). Note that PCU-UART does not implement the Data Carrier Detect (dcd_n) input.
6
0b
RO
Ring Indicator (RI):
This is used to indicate the current state of the modem control
line ri_n. This bit is the complement of ri_n. When the Ring Indicator input (ri_n) is
asserted it is an indication that a telephone ringing signal has been received by the
modem or data set. '0' - ri_n input is de-asserted (logic 1) '1' - ri_n input is asserted
(logic 0) In Loopback Mode (MCR[4] set to one), RI is the same as MCR[2] (Out1). Note
that PCU-UART does not implement the Ring Indicator (ri_n) input.
5
0b
RO
Data Set Ready (DSR):
This is used to indicate the current state of the modem control
line dsr_n. This bit is the complement of dsr_n. When the Data Set Ready input (dsr_n)
is asserted it is an indication that the modem or data set is ready to establish
communications with the DW_apb_uart. '0' - dsr_n input is de-asserted (logic 1) '1' -
dsr_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DSR is the
same as MCR[0] (DTR). Note that PCU-UART does not implement the Data Set Ready
(dsr_n) input.
4
0b
RO
Clear to Send (CTS):
This is used to indicate the current state of the modem control
line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is
asserted it is an indication that the modem or data set is ready to exchange data with
the DW_apb_uart. '0' - cts_n input is de-asserted (logic 1) '1' - cts_n input is asserted
(logic 0) In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS). Note that
PCU-UART does not implement the Clear to Send (cts_n) input.
3
0b
RO
Delta Data Carrier Detect (DDCD):
This is used to indicate that the modem control
line dcd_n has changed since the last time the MSR was read. '0' - no change on dcd_n
since last read of MSR '1' - change on dcd_n since last read of MSR Reading the MSR
clears the DDCD bit. In Loopback Mode (MCR[4] = 1), DDCD reflects changes on
MCR[3] (Out2). Note, if the DDCD bit is not set and the dcd_n signal is asserted (low)
and a reset occurs (software or otherwise), then the DDCD bit is set when the reset is
removed if the dcd_n signal remains asserted. Note that PCU-UART does not implement
the Data Carrier Detect (dcd_n) input.
2
0b
RO
Trailing Edge of Ring Indicator (TERI):
This is used to indicate that a change on the
input ri_n (from an active-low to an inactive-high state) has occurred since the last time
the MSR was read. '0' - no change on ri_n since last read of MSR '1' - change on ri_n
since last read of MSR Reading the MSR clears the TERI bit. In Loopback Mode (MCR[4]
= 1), TERI reflects when MCR[2] (Out1) has changed state from a high to a low. Note
that PCU-UART does not implement the Ring Indicator (ri_n) input.