Intel E3815 FH8065301567411 Ficha De Dados
Códigos do produto
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
569
14.10.122 MIPIC_LP_BYTECLK_REGISTER—Offset B860h
mipi C LP byteclk register
Access Method
Default: 00000000h
3
0b
RW
TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE:
Set by the
processor to enable or disable the error recovery action to be taken by the DSI Tx
controller if TxDSI data type not recognised error interrupt is cleared by the processor.
0 - Error recovery action will be taken if TxDSI data type not recognised error interrupt
is cleared by the processor.
1 - If TxDSI data type not recognised error interrupt is cleared by the processor, error
recovery action will not be taken by the DSI TX controller. Tx DSI data type not
recognized error interrupt will act as an informative interrupt
2
0b
RW
TXECC_MULTIBIT_ERR_RECOVERY_DISABLE:
Set by the processor to enable or
disable the error recovery action to be taken by the DSI Tx controller if Tx ECC multibit
error interrupt is cleared by the processor.
0 - Error recovery action will be taken if Tx ECC multibit error interrupt is cleared by the
processor.
1 - If Tx ECC multibit error interrupt is cleared by the processor, error recovery action
will not be taken by the DSI TX controller. Tx multibit error interrupt will act as an
informative interrupt
1
0b
RW
CLOCKSTOP:
Set by the processor to enable or disable clock stopping feature during
BLLP timing in a DPI transfer in dual channel mode or during DPI only mode and also
when there is no traffic in the DBI interface in DBI only enabled mode. By default this
register value is 0.
0 - clock stopping disabled
1 - clock stopping enabled
0
0b
RW
EOT_DIS:
Set by the processor to enable or disable EOT short packet transmission. By
default this register value is 0. For backward comapatibility of earlier DSI systems, EOT
short packet transmission can be disabled.
0 - EOT short packet transmission enabled
1 - EOT short packet transmission disabled
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RES
E
RV
ED
LP_BYT
ECLK
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0b
RW
RESERVED:
Reserved.
15:0
0b
RW
LP_BYTECLK:
Low power clock equivalence in terms of byte clock. The value
programmed in this register is equal to the number of byte clocks occupied in one low
power clock. This value is based on the byte clock (txbyteclkhs) and low power clock
frequency (txclkesc)