Intel E3815 FH8065301567411 Ficha De Dados
Códigos do produto
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1767
16.6.4
Argument 1 Register (ARGUMENT)—Offset 8h
This register contains the SD Command Argument.
Access Method
Default: 00000000h
16.6.5
Transfer Mode Register (TX_MODE)—Offset Ch
This register is used to control the operation of data transfers. The Host Driver shall set
this register before issuing a command which transfers data (Refer to Data Present
Select in the Command register), or before issuing a Resume command. The Host
Driver shall save the value of this register when the data transfer is suspended (as a
result of a Suspend command) and restore it before issuing a Resume command. To
prevent data loss, the Host Controller shall implement write protection for this register
during data transactions. Writes to this register shall be ignored when the Command
Inhibit (DAT) in the Present State register is 1.
Access Method
Bit
Range
Default &
Access
Field Name (ID): Description
15:0
0000h
RW
Blocks Count For Current Transfer (blk_count):
This register is enabled when Block
Count Enable in the Transfer Mode register is set to 1, and is valid only for multiple block
transfers. The Host Driver shall set this register to a value between 1 and the maximum
block count. The HC decrements the block count after each block transfer, and stops
when the count reaches zero. Setting the block count to 0 results in no data blocks
being transferred. This register should be accessed only when no transaction is
executing (i.e., after transactions are stopped). During data transfer, read operations on
this register may return an invalid value and write operations are ignored. When saving
transfer context as a result of a Suspend command, the number of blocks yet to be
transferred can be determined by reading this register. When restoring transfer context
prior to issuing a Resume command, the HD shall restore the previously saved block
count.
•
•
0000h = Stop Count
•
0001h = 1 block
•
0002h = 2 blocks
•
. . .
•
FFFFh = 65535 blocks
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:17, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ar
gument
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0h
RW
Command Argument 1 (argument):
The SD Command Argument is specified as
bit39-8 of Command-Format in the Physical Layer Specification.