Intel N2820 FH8065301616603 Ficha De Dados
Códigos do produto
FH8065301616603
Low Power Engine (LPE) for Audio (I
2
S)
716
Datasheet
16.7.2.2
Peripheral Trailing Byte Interrupt
It is possible for the DMA to reach the end of its Descriptor chain while removing
Receive FIFO data. When this happens, the processor is forced to take over because
the DMA can no longer service the Enhanced SSP request until a new chain is linked.
When the DMA has reached the end of its Descriptor chain, and there is data in the
receive FIFO, the Enhanced SSP will do the following:
Receive FIFO data. When this happens, the processor is forced to take over because
the DMA can no longer service the Enhanced SSP request until a new chain is linked.
When the DMA has reached the end of its Descriptor chain, and there is data in the
receive FIFO, the Enhanced SSP will do the following:
•
Sets the peripheral trailing byte interrupt SSSR.PINT bit to 1
•
Asserts the Enhanced SSP Interrupt to signal to the processor that a Peripheral
Trailing Byte Interrupt condition has occurred (if SSCR1.PINTE=1 to enable the
interrupt).
Trailing Byte Interrupt condition has occurred (if SSCR1.PINTE=1 to enable the
interrupt).
•
Sets the SSSR.EOC status bit which must be cleared by software. If more data is
received after the EOC bit was set (and EOC bit is still set), then the SSSR.PINT bit
will be set to a 1.
received after the EOC bit was set (and EOC bit is still set), then the SSSR.PINT bit
will be set to a 1.
Once the SSSR.PINT bit is set, it must be cleared by software by writing a 1 to it.
Clearing the SSSR.PINT bit also de-asserts the Peripheral Interrupt if it has been
enabled (SSCR1.PINTE=1).
Clearing the SSSR.PINT bit also de-asserts the Peripheral Interrupt if it has been
enabled (SSCR1.PINTE=1).
The remaining bytes must then be removed by means of a processor I/O as described
in the processor-based method below, or by reprogramming a new Descriptor chain
and restarting the DMA. Programmers need to be aware of this possibility. Refer to the
DMA chapter for details on Descriptor programming and “end of chain” events.
in the processor-based method below, or by reprogramming a new Descriptor chain
and restarting the DMA. Programmers need to be aware of this possibility. Refer to the
DMA chapter for details on Descriptor programming and “end of chain” events.
16.7.2.3
Removing Trailing Bytes (Processor Based SSCR1.TRAIL=0)
This is the default method indicated by a zero in the SSCR1.TRAIL bit. In this case, no
Receive DMA service request is generated. To read out the trailing bytes, software
should wait for the timeout Interrupt and then read all remaining entries as indicated
by the SSSR.RFL and SSSR.RNE bits within the Enhanced SSP Status register (SSSR).
Receive DMA service request is generated. To read out the trailing bytes, software
should wait for the timeout Interrupt and then read all remaining entries as indicated
by the SSSR.RFL and SSSR.RNE bits within the Enhanced SSP Status register (SSSR).
Note:
To use the Trailing bytes feature through the CPU, the Timeout Interrupt must be
enabled by setting SSCR1.TINTE=1 (to enable the interrupt).
16.7.2.4
Removing Trailing Bytes (DMA Based SSCR1.TRAIL=1)
When the DMA is to handle trailing bytes (SSCR1.TRAIL = 1) a DMA service request is
automatically issued for the remaining number of samples left in the Receive buffer.
The DMA will then empty the contents of the Receive buffer unless the DMA reaches the
end of its Descriptor chain
automatically issued for the remaining number of samples left in the Receive buffer.
The DMA will then empty the contents of the Receive buffer unless the DMA reaches the
end of its Descriptor chain
.
If a timeout occurs, the processor is only interrupted by
means of a Timeout Interrupt if it has been enabled by setting SSCR1.TINTE=1. When
handling trailing bytes by means of the DMA, if a timeout occurs and the receive FIFO is
empty, an End-of-Receive (EOR) will be sent to the DMA Controller. If an EOC occurs at
the time that the last sample is read out of the FIFO (the DMA descriptor chain was just
exactly long enough), and the timeout counter is still running (that is, a time out has
not occurred and the SSTO register is non-zero), then, when the time out does occur,
the Enhanced SSP will generate a DMA request which will create an RAS interrupt from
the DMA. When this occurs, software must re-program the DMA registers and re-enable
the channel for the Enhanced SSP to send its EOR to the DMA controller.
handling trailing bytes by means of the DMA, if a timeout occurs and the receive FIFO is
empty, an End-of-Receive (EOR) will be sent to the DMA Controller. If an EOC occurs at
the time that the last sample is read out of the FIFO (the DMA descriptor chain was just
exactly long enough), and the timeout counter is still running (that is, a time out has
not occurred and the SSTO register is non-zero), then, when the time out does occur,
the Enhanced SSP will generate a DMA request which will create an RAS interrupt from
the DMA. When this occurs, software must re-program the DMA registers and re-enable
the channel for the Enhanced SSP to send its EOR to the DMA controller.