Intel N2820 FH8065301616603 Ficha De Dados

724

Datasheet

If SLCTL.PDE and SLTCTL.HPE are both set, and STSTS.PDC transitions from 0 to 1, an 
interrupt will be generated.

System Error events are support by both internal and external sources. See the PCI 
Express* Base Specification, Revision 2.0 for details.

Each root port’s link supports L0s, L1, and L2/3 link states per PCI Express* Base 
Specification, Revision 2.0. L2/3 is entered on entry to S3.

PCI Express* Base Specification, Rev. 2.0

Each root port supports its own extended PCI bridge header in PCI configuration space. 
These headers are located on PCI bus 0, device 28, functions 0-32 as shown below. 
There are no other registers implemented by the root ports or their controller.

See Chapters 

 for additional information.