Intel N2820 FH8065301616603 Ficha De Dados
Códigos do produto
FH8065301616603
PCU – iLB – Interrupt Decoding and Routing
1266
Datasheet
30
PCU – iLB – Interrupt Decoding
and Routing
The interrupt decoder is responsible for receiving interrupt messages from other
devices in the processor and decoding them for consumption by the interrupt router,
the
devices in the processor and decoding them for consumption by the interrupt router,
the
The interrupt router is responsible for mapping each incoming interrupt to the
appropriate PIRQx, for consumption by the
appropriate PIRQx, for consumption by the
30.1
Features
30.1.1
Interrupt Decoder
The interrupt decoder receives interrupt messages from devices in the processor. These
interrupts can be split into two primary groups:
interrupts can be split into two primary groups:
•
For consumption by the interrupt router
•
For consumption by the 8259 PIC
30.1.1.1
For Consumption by the Interrupt Router
When a PCI-mapped device in the processor asserts or de-asserts an INT[A:D]
interrupt, an interrupt message is sent to the decoder. This message is decoded to
indicate to the interrupt router which specific interrupt is asserted or de-asserted and
which device the INT[A:D] interrupt originated from.
interrupt, an interrupt message is sent to the decoder. This message is decoded to
indicate to the interrupt router which specific interrupt is asserted or de-asserted and
which device the INT[A:D] interrupt originated from.
30.1.1.2
For Consumption by the 8259 PIC
When a device in the processor asserts or de-asserts a legacy interrupt (IRQ), an
interrupt message is sent to the decoder. This message is decoded to indicate to the
8259 PIC which specific interrupt (IRQ[3, 4, 14 or 15]) was asserted or de-asserted.
interrupt message is sent to the decoder. This message is decoded to indicate to the
8259 PIC which specific interrupt (IRQ[3, 4, 14 or 15]) was asserted or de-asserted.
30.1.2
Interrupt Router
The interrupt router aggregates the INT[A:D] interrupts for each PCI-mapped device in
the processor, received from the interrupt decoder, and the INT[A:D] interrupts direct
from the Serialized IRQ controller. It then maps these aggregated interrupts to 8 PCI
based interrupts: PIRQ[A:H]. This mapping is configured using the IR[31:0] registers.
the processor, received from the interrupt decoder, and the INT[A:D] interrupts direct
from the Serialized IRQ controller. It then maps these aggregated interrupts to 8 PCI
based interrupts: PIRQ[A:H]. This mapping is configured using the IR[31:0] registers.
PCI based interrupts PIRQ[A:H] are then available for consumption by either the 8259
PICs or the IO-APIC, depending on the configuration of the 8 PIRQx Routing Control
Registers: PIRQA, PIQRB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, PIRQH.
PICs or the IO-APIC, depending on the configuration of the 8 PIRQx Routing Control
Registers: PIRQA, PIQRB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, PIRQH.