VXi SM7100 Manual Do Utilizador
VXI Technology, Inc.
32
SM7100 Programming
Delay Register - Read and Write
ADDR
Plug-In LA+0x202
D15-D0
Data Bus
16 Bit
This register is used to set the time that the plug-in module will hold the Board
Busy signal active. The Board Busy signal is set every time the plug-in receives a
Write to a relevant Relay Register memory space. The Board Busy signal will be
removed at the end of the time out that is set by the value contained in this register.
For each count loaded into this register, the Board Busy signal will be held active
for 1 µs. The delay may be set from 0 to approximately 65 ms, thus accommodating
a wide variation in test station requirements.
The Board Busy signal may be monitored by the user, in either a polled or an
interrupt fashion, and is to be used as an indication that the relays in the newly
actuated path have settled. Alternatively, the Board Busy signal may also be used to
drive the TTL Trigger Bus. See the Board Busy, Interrupt Control and Busy
Trigger Control Register descriptions in the A16 address space.
Busy signal active. The Board Busy signal is set every time the plug-in receives a
Write to a relevant Relay Register memory space. The Board Busy signal will be
removed at the end of the time out that is set by the value contained in this register.
For each count loaded into this register, the Board Busy signal will be held active
for 1 µs. The delay may be set from 0 to approximately 65 ms, thus accommodating
a wide variation in test station requirements.
The Board Busy signal may be monitored by the user, in either a polled or an
interrupt fashion, and is to be used as an indication that the relays in the newly
actuated path have settled. Alternatively, the Board Busy signal may also be used to
drive the TTL Trigger Bus. See the Board Busy, Interrupt Control and Busy
Trigger Control Register descriptions in the A16 address space.
Status Register - Read Only
ADDR
Plug-In LA+0x204
D15-D13
Hardware
Revision
Code
D12-D1 Unused
D0
Front Panel
Open
signal set
by this
module
0 = Indicates that the module's Front Panel Open signal was not activated by the
user
1 = An indication that the module's Front Panel Open signal was activated as
programmed by the user
Pon state = 0
A read of this bit location will indicate whether the Front Panel Open signal was
triggered from the front panel of the module. A read of this register clears this bit to
0.
A read of this bit location will indicate whether the Front Panel Open signal was
triggered from the front panel of the module. A read of this register clears this bit to
0.