Xilinx V2.1 Manual Do Utilizador
Memory
109
Xilinx Blocks
Other parameters used by this block are explained in the Common Parameters section
of the previous chapter.
of the previous chapter.
Xilinx LogiCORE
The block always uses a Xilinx LogiCORE: Single Port Block Memory V3.2 or
Distributed Memory V5.0. For the block memory, the address width must be equal to
Distributed Memory V5.0. For the block memory, the address width must be equal to
where d denotes the memory depth.
The tables below indicate the widths that are acceptable for each depth.
When the distributed memory parameter is selected, LogiCORE Distributed Memory
V5.0 is used. The depth must be between 16 and 65536, inclusive for Virtex-II and
V5.0 is used. The depth must be between 16 and 65536, inclusive for Virtex-II and
Table: Maximum Word Width for Various Depth Ranges (Virtex/Virtex-E)
Depth
Width
2 to 512
256
513 to 1024
256
1025 to 2048
256
2049 to 4096
192
4097 to 8192
96
8193 to 16K
48
16K+1 to 32K
24
32K+1 to 64K
12
64K+1 to 128K
6
128K+1 to 256K
3
Table: Maximum Word Width for Various Depth Ranges (Virtex-II)
Depth
Width
2 to 512
256
513 to 1024
256
1025 to 2048
256
2049 to 4096
256
4097 to 8192
256
8193 to 16K
192
16K+1 to 32K
96
32K+1 to 64K
48
64K+1 to 128K
24
128K+1 to 256K
12
256K+1 to 512K
6
512K+1 to 1024K
3
d
2
log