Ricoh R5C841 Manual Do Utilizador

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2004

 

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On no use of ports, TPBP* and TPBN* are directly connected to AGND, and TPAP*, TPAN* and 

TPBIAS* are OPEN. After that, set Port Disable bit of the 1394 PHY Register. The PHY Shadow 

register in the 1394 Configuration registers space also can set the Port disable bit. See the 

Read/Write of the 1394PHY register (Ch. 4.22.4). 

The R5C841 builds in a function monitoring the state of the cable power. The CPS pin is 

connected to the cable power through the external resistor (390k

Ω

±1%) and detects a condition 

that cable power has lowered under the threshold level (Normally 7.5V). When the four pins cable 

is used (when the CPS function is not used), it is possible to select two methods: one is the direct 

connection of the CPS pin with the AVCC_PHY3V, and the other is with the register’s control of 

the CPS pin which is set to ‘Open’. In case of the register’s control, set CPSDis (bit1) and 

CPSFixVal (bit0) on the PHY Power Management Register (98h) in the 1394 Configuration 

Register space to “1b”. The Serial ROM also can be set these registers. Refer to the Serial ROM 

(Chapter 4.20) for details. 
 

On monitoring the state of Cable Power. 

Cable power supply 

R5C841 390kohm(±1%)  6pin 

connector 

CPS VP 

Out of monitoring the state of Cable Power.   

R5C841 AVCC_PHY3V 

4pin 

connector 

CPS 

 

 

The R5C841 builds in the 1394 PHY registers compliant with IEEE 1394-1995 and 

IEEE1394a-2000 standard. Refer to the 1394PHY Registers for details. Access to these registers 

is enabled by the PHY Control register of the 1394 OHCI Registers, and offsetting [31-11] bits of 

the 1394 OHCI Register Base Address (10h) in the 1394 Configuration register space enables 

access to the PHY Control register (0ECh).   

The data of 1394 PHY register is the little endian description. On access of the PHY Control 

register, the R5C841 converts the data from a little endian to a bit endian. So the data is dealt 

only in a row without the bit number of data.   

 

P H Y   R eg iste r 
 

0   1   2 3   4  5   6  7  

 
P H Y   C on trol 

 

rd D a ta    

2 3  2 2  2 1  2 0   1 9  1 8  1 7  1 6  

 
 

w rD a ta  

7   6   5 4   3  2   1  0