Philips 8-bit microcontroller with two-clock 80C51 core UM10109 Manual Do Utilizador
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
User manual
Rev. 02 — 23 May 2005
105 of 133
Philips Semiconductors
UM10109
P89LPC932A1 User manual
16.1 Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,
as if an external reset or watchdog reset had occurred. If a value is written to AUXR1 that
contains a 1 at bit position 3, all SFRs will be initialized and execution will resume at
program address 0000. Care should be taken when writing to AUXR1 to avoid accidental
software resets.
as if an external reset or watchdog reset had occurred. If a value is written to AUXR1 that
contains a 1 at bit position 3, all SFRs will be initialized and execution will resume at
program address 0000. Care should be taken when writing to AUXR1 to avoid accidental
software resets.
16.2 Dual Data Pointers
The dual Data Pointers (DPTR) adds to the ways in which the processor can specify the
address used with certain instructions. The DPS bit in the AUXR1 register selects one of
the two Data Pointers. The DPTR that is not currently selected is not accessible to
software unless the DPS bit is toggled.
address used with certain instructions. The DPS bit in the AUXR1 register selects one of
the two Data Pointers. The DPTR that is not currently selected is not accessible to
software unless the DPS bit is toggled.
Specific instructions affected by the Data Pointer selection are:
INC DPTR — Increments the Data Pointer by 1
JMP@A+DPTR — Jump indirect relative to DPTR value
MOV DPTR, #data16 — Load the Data Pointer with a 16-bit constant
MOVC A, @A+DPTR — Move code byte relative to DPTR to the accumulator
MOVX A, @DPTR — Move accumulator to data memory relative to DPTR
MOVX @DPTR, A — Move from data memory relative to DPTR to the accumulator
Also, any instruction that reads or manipulates the DPH and DPL registers (the upper and
lower bytes of the current DPTR) will be affected by the setting of DPS. The MOVX
instructions have limited application for the P89LPC932A1 since the part does not have
an external data bus. However, they may be used to access Flash configuration
information (see Flash Configuration section) or auxiliary data (XDATA) memory.
lower bytes of the current DPTR) will be affected by the setting of DPS. The MOVX
instructions have limited application for the P89LPC932A1 since the part does not have
an external data bus. However, they may be used to access Flash configuration
information (see Flash Configuration section) or auxiliary data (XDATA) memory.
Bit 2 of AUXR1 is permanently wired as a logic 0. This is so that the DPS bit may be
toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,
without the possibility of inadvertently altering other bits in the register.
toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,
without the possibility of inadvertently altering other bits in the register.
17. Data EEPROM
The P89LPC932A1 has 512 bytes of on-chip Data EEPROM that can be used to save
configuration parameters. The Data EEPROM is SFR based, byte readable, byte writable,
and erasable (via row fill and sector fill). The user can read, write, and fill the memory via
three SFRs and one interrupt:
configuration parameters. The Data EEPROM is SFR based, byte readable, byte writable,
and erasable (via row fill and sector fill). The user can read, write, and fill the memory via
three SFRs and one interrupt:
•
Address Register (DEEADR) is used for address bits 7 to 0 (bit 8 is in the DEECON
register).
register).
•
Control Register (DEECON) is used for address bit 8, setup operation mode, and
status flag bit (see
status flag bit (see
).
•
Data Register (DEEDAT) is used for writing data to, or reading data from, the Data
EEPROM.
EEPROM.