LSI 53C810A Manual Do Utilizador
Index
IX-3
I
I/O bit
I/O instructions
I_O bit
IARB bit
IDSEL
IID bit
,
illegal instruction detected bit
,
immediate arbitration bit
initialization device select
initiator mode
phase mismatch
initiator ready
input
instructions
block move
I/O
load and store
memory move
read/write
transfer control
interrupt
line
pin (IP[7:0])
interrupt status register
interrupt-on-the-fly bit
interrupts
fatal vs. nonfatal interrupts
halting
IRQ disable bit
masking
polling vs. hardware
registers
stacked interrupts
INTF bit
IRDY/
IRQ disable bit
IRQ mode bit
IRQD bit
IRQM bit
ISTAT register
L
last disconnect bit
latched SCSI parity bit
latency
timer (LT[7:0])
LDSC bit
LOA bit
load and store instructions
no flush option
prefetch unit and store instructions
lost arbitration bit
LOW bit
LSI53C700 family compatibility bit
LSI53C810A
ease of use
flexibility
integration
performance
reliability
testability
M
M/A bit
,
MACNTL register
MAN bit
manual start mode bit
MASR bit
master control for set or reset pulses bit
master data parity error bit
MDPE bit
master enable bit
master parity error enable bit
max SCSI synchronous offset bits
max_lat (ML[7:0])
MDPE bit
memory access control register
memory move instructions
and SCRIPTS instruction prefetching
no flush option
memory read line command
memory read multiple command
memory write and invalidate command
write and invalidate mode bit
min_gnt (MG[7:0])
move to/from SFBR cycles
MPEE bit
MSG bit
,
,
N
NFMMOV instruction
no flush memory-to-memory move
O
OLF bit
opcode fetch bursting
operating registers
adder sum output
chip test five
chip test four
chip test one
chip test six
chip test three
chip test two
chip test zero
data structure address
DMA byte counter
DMA command
DMA control
DMA FIFO
DMA interrupt enable
DMA mode
DMA next address
DMA SCRIPTS pointer
DMA SCRIPTS pointer save
DMA status
general information
general purpose
general purpose pin control
interrupt status
memory access control
response ID zero
scratch register A
SCSI bus control lines