Hitachi 1000 Manual Do Utilizador
14
BladeSymphony 1000 Architecture
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• ECC — The ECC can correct an error in consecutive four bits in any four DIMM set (i.e., a fault in one
DRAM device). This function is equivalent to technology generally referred to as Chipkill and allows
the contents of memory to be reconstructed even if one chip completely fails. The concept is similar
to the way RAID protects content on disk drives.
the contents of memory to be reconstructed even if one chip completely fails. The concept is similar
to the way RAID protects content on disk drives.
• Memory device replacing function — The NDC and MC have a function to replace a faulty DRAM
device with a normal spare one assisted by the System Abstraction Layer (SAL) firmware. This keeps
the ECC function (S2EC-D2ED) operating. It can replace up to two DRAM devices in any one set of
four DIMMs.
the ECC function (S2EC-D2ED) operating. It can replace up to two DRAM devices in any one set of
four DIMMs.
• Memory hierarchy table (size, bandwidth/latency)
• L1 cache
• L2 cache
• L3 cache
• On board memory
• Off board memory
• Interleaved vs. non-interleaved memory configuration
• ccNUMA (cache coherent Non-uniform memory access) description
SMP Capabilities
While dual processors systems are now common place, increasing the number of processors/sockets
beyond two poses many challenges in computer design, particularly in the memory system. As
processors are added to a system the amount of contention for memory access quickly increases to
the point where the intended throughput improvement of more processors is significantly diminished.
The processors spend more time waiting for data to be supplied from memory than performing useful
computing tasks. Conventional uniform memory systems are not capable of scaling to larger numbers
of processors due to memory bus contention. Traditional large SMP systems introduce cross bar
switches in order to overcome this problem. However, this approach adds to the memory hierarchy,
system complexity, and physical size of the system. SMP systems typically do not possess the
advantages of blade systems, e.g., compact packaging and flexibility.
beyond two poses many challenges in computer design, particularly in the memory system. As
processors are added to a system the amount of contention for memory access quickly increases to
the point where the intended throughput improvement of more processors is significantly diminished.
The processors spend more time waiting for data to be supplied from memory than performing useful
computing tasks. Conventional uniform memory systems are not capable of scaling to larger numbers
of processors due to memory bus contention. Traditional large SMP systems introduce cross bar
switches in order to overcome this problem. However, this approach adds to the memory hierarchy,
system complexity, and physical size of the system. SMP systems typically do not possess the
advantages of blade systems, e.g., compact packaging and flexibility.
Leveraging their extensive mainframe design experience, Hitachi employs a number of advanced
design techniques to create a blade-based SMP system, allowing the BladeSymphony 1000 to scale
up to an eight socket, 16 core system with as much as 256 GB of memory. The heart of the design is
the Hitachi custom designed Node Controller, which effectively breaks a large system into smaller, more
flexible nodes or server blades in blade format. These server blades can act as complete, independent
systems or up to four server blades can be connected to form a single, efficient multi-processor
system, as illustrated in Figure 6.
design techniques to create a blade-based SMP system, allowing the BladeSymphony 1000 to scale
up to an eight socket, 16 core system with as much as 256 GB of memory. The heart of the design is
the Hitachi custom designed Node Controller, which effectively breaks a large system into smaller, more
flexible nodes or server blades in blade format. These server blades can act as complete, independent
systems or up to four server blades can be connected to form a single, efficient multi-processor
system, as illustrated in Figure 6.