ARM CM940T Manual Do Utilizador
Hardware Description
3-3
3.2
SSRAM controller
The SSRAM controller is implemented in a Xilinx 9572 PLD which enables the
SSRAM to achieve single-cycle operation. In addition to controlling accesses to the
SSRAM, the controller generates the processor response signals (BWAIT, BERROR,
BLAST) for all accesses to:
SSRAM to achieve single-cycle operation. In addition to controlling accesses to the
SSRAM, the controller generates the processor response signals (BWAIT, BERROR,
BLAST) for all accesses to:
•
SSRAM
•
SDRAM
•
status and configuration register space
•
system bus bridge.