ARM CM940T Manual Do Utilizador
Programmer’s Reference
4-6
4.2
Exception vector mapping
The convention for ARM cores is to map the exception vectors to begin at address 0.
However, the ARM940T core allows the vectors to be moved to 0xFFFF0000 by
writing to the V bit in coprocessor 15 register 1 (CP15c1). The value of the V bit at reset
is determined by the level on an external pin (VINITHI). To maintain compatibility
across all cores, the default reset value maps the vector to begin at address 0 (see the
ARM940T Technical Reference Manual).
However, the ARM940T core allows the vectors to be moved to 0xFFFF0000 by
writing to the V bit in coprocessor 15 register 1 (CP15c1). The value of the V bit at reset
is determined by the level on an external pin (VINITHI). To maintain compatibility
across all cores, the default reset value maps the vector to begin at address 0 (see the
ARM940T Technical Reference Manual).
When running applications with high vectors (at 0xFFFF0000 to 0xFFFFFFFF),
software must write the correct value to the coprocessor register. However, Integrator
motherboards have no physical memory at this location. This means that the MMU
must be programmed to map an area of physical memory to this virtual address. When
the core module is being used with a motherboard, an alternative is to implement an area
of physical memory on an expansion card or logic module.
software must write the correct value to the coprocessor register. However, Integrator
motherboards have no physical memory at this location. This means that the MMU
must be programmed to map an area of physical memory to this virtual address. When
the core module is being used with a motherboard, an alternative is to implement an area
of physical memory on an expansion card or logic module.