American Megatrends MegaRAID Express 500 Manual Do Utilizador
Chapter 4 Features
33
PCI Bridge/CPU
MegaRAID Express 500 uses the Intel i960RM PCI bridge with an embedded
80960JX RISC processor running at 100 MHz. The RM bridge handles data
transfers between the primary (host) PCI bus, the secondary PCI bus, cache
memory, and the SCSI bus. The DMA controller supports chaining and
unaligned data transfers. The embedded 80960JX CPU directs all controller
functions, including command processing, SCSI bus transfers, RAID processing,
drive rebuilding, cache management, and error recovery.
80960JX RISC processor running at 100 MHz. The RM bridge handles data
transfers between the primary (host) PCI bus, the secondary PCI bus, cache
memory, and the SCSI bus. The DMA controller supports chaining and
unaligned data transfers. The embedded 80960JX CPU directs all controller
functions, including command processing, SCSI bus transfers, RAID processing,
drive rebuilding, cache management, and error recovery.
Cache Memory
MegaRAID Express 500 cache memory resides in a memory bank that uses 2 M
x 72 (16 MB), 4 M x 72 (32 MB), 8 M x 72 (64 MB) or 16 M x 72 (128 MB)
unbuffered 3.3V SDRAM . Possible configurations are 8, 16, 32, 64, or 128 MB.
The maximum achievable memory bandwidth is 528 MB/s.
x 72 (16 MB), 4 M x 72 (32 MB), 8 M x 72 (64 MB) or 16 M x 72 (128 MB)
unbuffered 3.3V SDRAM . Possible configurations are 8, 16, 32, 64, or 128 MB.
The maximum achievable memory bandwidth is 528 MB/s.
MegaRAID Express 500 supports write-through or write-back caching,
selectable for each logical drive. To improve performance in sequential disk
accesses, the MegaRAID Express 500 controller uses read-ahead caching by
default. You can disable read-ahead caching.
selectable for each logical drive. To improve performance in sequential disk
accesses, the MegaRAID Express 500 controller uses read-ahead caching by
default. You can disable read-ahead caching.