Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 Manual Do Utilizador

Códigos do produto

BX80605X3430

Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

3.4.2.4

PCISTS—PCI Status Register ...................................................... 99

3.4.2.5

RID—Revision Identification Register ......................................... 101

3.4.2.6

CCR—Class Code Register ........................................................ 101

3.4.2.7

CLSR—Cacheline Size Register.................................................. 101

3.4.2.8

HDR—Header Type Register ..................................................... 102

3.4.2.9

SVID—Subsystem Vendor ID .................................................... 102

3.4.2.10 SID—Subsystem Device ID ...................................................... 102

3.4.2.11 CAPPTR—Capability Pointer ...................................................... 102

3.4.2.12 INTLIN—Interrupt Line Register ................................................ 103

3.4.2.13 INTPIN—Interrupt Pin Register ................................................. 103

3.4.3

Common Extended Configuration Space Registers..................................... 103
3.4.3.1

CAPID—PCI Express Capability List Register ............................... 103

3.4.3.2

NXTPTR—PCI Express Next Capability List Register...................... 104

3.4.3.3

EXPCAP—PCI Express Capabilities Register ................................. 104

3.4.3.4

DEVCAP—PCI Express Device Capabilities Register ...................... 105

3.4.3.5

DEVCTRL—PCI Express Device Control Register .......................... 106

3.4.3.6

DEVSTS—PCI Express Device Status Register ............................. 108

3.4.4

Intel

VT-d, Address Mapping, System Management Registers (Device 8,

Function 0).......................................................................................... 109
3.4.4.1

IIOMISCCTRL—Integrated I/O Misc Control Register .................... 109

3.4.4.2

IIOMISCSS—Integrated I/O MISC Status ................................... 110

3.4.4.3

TSEGCTRL—TSEG Control Register ............................................ 110

3.4.4.4

TOLM—Top of Low Memory ...................................................... 111

3.4.4.5

TOHM—Top of High Memory ..................................................... 111

3.4.4.6

NCMEM.BASE—NCMEM Base .................................................... 111

3.4.4.7

NCMEM.LIMIT—NCMEM Limit.................................................... 112

3.4.4.8

DEVHIDE1—Device Hide 1 Register ........................................... 112

3.4.4.9

DEVHIDE2—Device Hide 2 Register ........................................... 115

3.4.4.10 IIOBUSNO—IIO Internal Bus Number ........................................ 116

3.4.4.11 LMMIOL.BASE—Local MMIOL Base............................................. 116

3.4.4.12 LMMIOL.LIMIT—Local MMIOL Limit ............................................ 117

3.4.4.13 LMMIOH.BASE—Local MMIOH Base............................................ 117

3.4.4.14 LMMIOH.LIMIT—Local MMIOH Limit ........................................... 117

3.4.4.15 LMMIOH.BASEU—Local MMIOH Base Upper ................................ 118

3.4.4.16 LMMIOH.LIMITU—Local MMIOH Limit Upper................................ 118

3.4.4.17 LCFGBUS.BASE—Local Configuration Bus Number Base Register ... 118

3.4.4.18 LCFGBUS.LIMIT—Local Configuration Bus Number Limit Register... 119

3.4.4.19 GMMIOL.BASE—Global MMIOL Base .......................................... 119

3.4.4.20 GMMIOL.LIMIT—Global MMIOL Limit.......................................... 119

3.4.4.21 GMMIOH.BASE—Global MMIOH Base ......................................... 120

3.4.4.22 GMMIOH.LIMIT—Global MMIOH Limit......................................... 120

3.4.4.23 GMMIOH.BASEU—Global MMIOH Base Upper .............................. 120

3.4.4.24 GMMIOH.LIMITU—Global MMIOH Limit Upper ............................. 121

3.4.4.25 GCFGBUS.BASE—Global Configuration Bus Number Base Register . 121

3.4.4.26 GCFGBUS.LIMIT—Global Configuration Bus Number Limit Register. 121

3.4.4.27 MESEGBASE—Intel

Management Engine (Intel

ME)

Memory Region Base............................................................... 122

3.4.4.28 MESEGMASK—Intel

ME Memory Region Mask ........................... 122

3.4.4.29 VTBAR—Base Address Register for Intel

VT-d Chipset Registers .. 122

3.4.4.30 VTGENCTRL—Intel

VT-d General Control Register...................... 123

3.4.4.31 VTISOCHCTRL—Intel VT-d Isoch Related Control Register ............ 124

3.4.4.32 VTGENCTRL2—Intel VT-d General Control 2 Register ................... 124

3.4.4.33 VTSTS—Intel

VT-d Status Register .......................................... 125

3.4.5

Semaphore and ScratchPad Registers (Dev:8, F:1) ................................... 125
3.4.5.1

SR[0:3]—Scratch Pad Register 0-3 (Sticky) ................................ 125

3.4.5.2

SR[4:7]—Scratch Pad Register 4-7 (Sticky) ................................ 125

3.4.5.3

SR[8:11]—Scratch Pad Register 8-11 (Non-Sticky)...................... 125

3.4.5.4

SR[12:15]—Scratch Pad Register 12-15 (Non-Sticky) .................. 126

3.4.5.5

SR[16:17]—Scratch Pad Register 16-17 (Non-Sticky) .................. 126

3.4.5.6

SR[18:23]—Scratch Pad Register 18-23 (Non-Sticky) .................. 126

3.4.5.7

CWR[0:3]—Conditional Write Registers 0-3 ................................ 126