Intel Pentium 4 RK80531PC033G0K Manual Do Utilizador
Códigos do produto
RK80531PC033G0K
Intel
®
Pentium
®
4 Processor in the 423-pin Package
16
TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die
termination. Inputs and used outputs must be terminated on the system board. Unused outputs may
be terminated on the system board or left unconnected. Note that leaving unused output not
terminated may interfere with some TAP functions, complicate debug probing, and prevent
boudary scan testing. Signal termination for these signal types is discussed in the Intel
termination. Inputs and used outputs must be terminated on the system board. Unused outputs may
be terminated on the system board or left unconnected. Note that leaving unused output not
terminated may interfere with some TAP functions, complicate debug probing, and prevent
boudary scan testing. Signal termination for these signal types is discussed in the Intel
®
Pentium
®
4 Processor and Intel
®
850 Chipset Platform Design Guide and ITP700 Debug Port Design Guide.
The TESTHI[10:0] pins must be connected to V
CC
via a pull-up resistor. TESTHI[10:0] may be
connected individually to V
CC
via pull-up resistors between 1 k
Ω
and 10 k
Ω
value. Alternately,
TESTHI[1:0] may be tied together and pulled up to V
CC
with a single 1 k
Ω
- 4.7 k
Ω
resistor;
TESTHI[7:2] may be tied together and pulled up to V
CC
with a single 1 k
Ω
- 4.7 k
Ω
resistor; and
TESTHI[10:8] may be tied together and pulled up to V
CC
with a single 1 k
Ω
- 4.7 k
Ω
resistor.
However, tying any of the TESTHI pins together will prevent the ability to perform boundary scan
testing.
testing.
2.6
System Bus Signal Groups
In order to simplify the following discussion, the system bus signals have been combined into
groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as
a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as
well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+
output group as well as the AGTL+ I/O group when driving.
groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as
a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as
well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+
output group as well as the AGTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify two sets of
timing parameters. One set is for common clock signals which are dependant upon the rising edge
of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals
which are relative to their respective strobe lines (data and address) as well as the rising edge of
BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at
any time during the clock cycle. Table 3 identifies which signals are common clock, source
synchronous, and asynchronous.
timing parameters. One set is for common clock signals which are dependant upon the rising edge
of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals
which are relative to their respective strobe lines (data and address) as well as the rising edge of
BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at
any time during the clock cycle. Table 3 identifies which signals are common clock, source
synchronous, and asynchronous.
Table 3. System Bus Pin Groups (Page 1 of 2)
Signal Group
Type
Signals
1
AGTL+ Common Clock Input
Synchronous
to BCLK[1:0]
to BCLK[1:0]
BPRI#, DEFER#, RESET#
2
, RS[2:0]#, RSP#, TRDY#
AGTL+ Common Clock I/O
Synchronous
to BCLK[1:0]
to BCLK[1:0]
AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#
2
, BR0#
2
,
DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#,
MCERR#
MCERR#
AGTL+ Source Synchronous I/O
Synchronous
to assoc.
strobe
to assoc.
strobe
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#
5
ADSTB0#
A[35:17]#
5
ADSTB1#
D[15:0]#, DBI0#
DSTBP0#, DSTBN0#
D[31:16]#, DBI1#
DSTBP1#, DSTBN1#
D[47:32]#, DBI2#
DSTBP2#, DSTBN2#
D[63:48]#, DBI3#
DSTBP3#, DSTBN3#