Intel Xeon X3470 BX80605X3470 Manual Do Utilizador

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Intel® Xeon® Processor 3400 Series Datasheet, Volume 1

The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge 
structure.

.

PCI Express extends the configuration space to 4096 bytes per-device/function, as 
compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express 
configuration space is divided into a PCI-compatible region (which consists of the first 
256 B of a logical device's configuration space) and an extended PCI Express region 
(which consists of the remaining configuration space). The PCI-compatible region can 
be accessed using either the mechanisms defined in the PCI specification or using the 
enhanced PCI Express configuration access mechanism described in the PCI Express 
Enhanced Configuration Mechanism section.

The PCI Express Host Bridge is required to translate the memory-mapped PCI Express 
configuration space accesses from the host processor to PCI Express configuration 
cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is 
recommended that system software access the enhanced configuration space using 32-
bit operations (32-bit aligned) only.

See the PCI Express Base Specification for details of both the PCI-compatible and PCI 
Express Enhanced configuration mechanisms and transaction rules.

The PCI Express interface on the processor is a single 16 lane (x16) port that can also 
be configured at narrower widths. It may be bifurcated (refer to 

port may train to narrower widths. The PCI Express port is designed to be compliant 
with the PCI Express Base Specification rev 2.0

PCI-PCI 

Bridge 

representing 

root PCI 

Express port 

(Device 3)

PCI-PCI 

Bridge 

representing 

root PCI 

Express port 

(Device 5)

PCI 

Compatible 

Host Bridge 

Device

(Device 0)