Motorola DSP56012 Manual Do Utilizador

Figure 4-15  Interrupt Vector Register Read Timing

Figure 4-16  HI Interrupt Structure

3. When HOREQ and HACK are asserted simultaneously, 
the contents of the IVR are placed on the host data bus.

2. The host processor asserts HACK with its interrupt 
acknowledge cycle.

1 K

DSP56012

IPL2
IPL1
IPL0

D0–D7

HOREQ

HACK

H0–H7

IACK

LOGIC

$0F

$3

+5 V

Interrupt Vector Number

Interrupt Vector Register (IVR)
(Read/Write)

MC68000

1. The DSP56012 Asserts HOREQ to interrupt the host 
processor.

IACK

Interrupt
Vector 
Register
(IVR)

AA0323.11

7

0

AS

FC0–FC2

A1–A31

HOREQ Asserted

HOREQ

AA0324k

Status

$2

Mask

HOREQ

HF3

HF2

TRDY TXDE RXDF

7

0

0

DMA

ICR

$3

INIT

HF1

HF0

0

TREQ RREQ

7

0

HM0

HM1

ISR

interrupt Source