Renesas R5S72641 Manual Do Utilizador
Section 18 Serial Sound Interface
R01UH0134EJ0400 Rev. 4.00
Page 913 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
2
RIE
0
R/W
Receive Interrupt Enable
Enables or disables generation of receive data full
interrupt (RXI) requests when the RDF flag in the FIFO
status register (SSIFSR) is set to 1 during reception.
interrupt (RXI) requests when the RDF flag in the FIFO
status register (SSIFSR) is set to 1 during reception.
0: Receive data full interrupt (RXI) request is disabled
1: Receive data full interrupt (RXI) request is enabled*
Note: * RXI can be cleared by clearing either the RDF
flag (see the description of the RDF bit for
details) or RIE bit.
details) or RIE bit.
1 TFRST
0 R/W
Transmit FIFO Data Register Reset
Invalidates the data in the transmit FIFO data register
(SSIFTDR) to reset the FIFO to an empty state.
(SSIFTDR) to reset the FIFO to an empty state.
0: Reset is disabled.
1: Reset is enabled.
Note: FIFO is reset at a power-on reset.
0 RFRST
0 R/W
Receive FIFO Data Register Reset
Invalidates the data in the receive FIFO data register
(SSIFRDR) to reset the FIFO to an empty state.
(SSIFRDR) to reset the FIFO to an empty state.
0: Reset is disabled
1: Reset is enabled
Note: FIFO is reset at a power-on reset.