Xilinx PCI32 Manual Do Utilizador
PCI32 Interface v3.0
DS206 August 31, 2005
5
Product Specification v3.0.151
illustrates a user application and the PCI Interface partitioned into five major blocks.
PCI I/O Interface Block
The I/O interface block handles the physical connection to the PCI bus including all signaling, input
and output synchronization, output three-state controls, and all request-grant handshaking for bus
mastering.
and output synchronization, output three-state controls, and all request-grant handshaking for bus
mastering.
User Application
The PCI Interface provides a simple, general-purpose interface for a wide range of applications.
PCI Configuration Space
This block provides the first 64 bytes of Type 0, version 3.0 Configuration Space Header, as shown in
, to support software-driven Plug-and-Play initialization and configuration. This includes infor-
mation for Command and Status, and three Base Address Registers (BARs).
The capability for extending configuration space has been built into the user application interface. This
capability, including the ability to implement a capabilities pointer in configuration space, allows the
user to implement functions such as power management and message signaled interrupts in the user
application.
capability, including the ability to implement a capabilities pointer in configuration space, allows the
user to implement functions such as power management and message signaled interrupts in the user
application.
Parity Generator/Checker
This block generates and checks even parity across the AD bus, the CBE# lines, and the parity signals.
It also reports data parity errors via PERR# and address parity errors via SERR#.
It also reports data parity errors via PERR# and address parity errors via SERR#.
Initiator State Machine
This block controls the PCI interface initiator functions. The states implemented are a subset of those
defined in Appendix B of the PCI Local Bus Specification. The initiator control logic uses one-hot encod-
ing for maximum performance.
defined in Appendix B of the PCI Local Bus Specification. The initiator control logic uses one-hot encod-
ing for maximum performance.
Figure Top x-ref 1
Figure 1: PCI Interface Block Diagram
Parity
Generator/
Checker
P C I C o n f i g u ra t i o n S p a c e
Initiator
State
Machine
Interrupt
Pin and
Line
Register
Latency
Timer
Register
Vendor ID,
Rev ID,
Other User
Data
Target
State
Machine
PCI I/O INTERF
A
CE
USER APPLICA
TION
A D I O [ 6 3 : 0 ]
A D [ 6 3 : 0 ]
PAR
GNT-
PERR-
SERR-
FRAME-
IRDY-
REQ-
TRDY-
DEVSEL-
STOP-
Base
Address
Register
0
Base
Address
Register
1
Command/
Status
Register
Base
Address
Register
2
REQ64-
ACK64-
PAR64
ADIO[63:0]