Freescale Semiconductor MCF52211 Manual Do Utilizador
General Purpose I/O Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
13-5
13.6.2
Port Data Direction Registers (DDRn)
The DDRn registers control the direction of the port n pin drivers when the pins are configured for digital
I/O.
I/O.
The DDRn registers with a full 8-bit implementation are shown in
registers use fewer than eight bits. Their bit definitions are shown in
,
, and
, which applies to all DDRn
registers.
The DDRn registers are read/write. At reset, all bits in the DDRn registers are cleared.
IPSBAR
Offset: 0x10_000C (PORTQS)
Access: User read/write
7
6
5
4
3
2
1
0
R
0
PORTn6
PORTn5
PORTn4
PORTn3
PORTn2
PORTn1
PORTn0
W
Reset:
0
1
1
1
1
1
1
1
Figure 13-4. Port QS Output Data Register (PORTQS)
IPSBAR
Offset: 0x10_0008 (PORTNQ)
Access: User read/write
7
6
5
4
3
2
1
0
R
PORTn7
PORTn6
PORTn5
PORTn4
PORTn3
PORTn2
PORTn1
0
W
Reset:
1
1
1
1
1
1
1
0
Figure 13-5. Port NQ Output Data Register (PORTNQ)
IPSBAR
Offset: 0x10_000B (PORTAS)
Access: User read/write
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
PORTn1
PORTn0
W
Reset:
0
0
0
0
0
0
1
1
Figure 13-6. Port AS Output Data Register (PORTAS)
Table 13-2. PORTn Field Descriptions
Field
Description
Portnx
Data to be driven when the port pin is configured as a digital output.
1 Output is a logic 1
0 Output is a logic 0
1 Output is a logic 1
0 Output is a logic 0