Freescale Semiconductor MCF52211 Manual Do Utilizador

19-8

Freescale Semiconductor

 

Prior to issuing any program or erase commands, the clock configuration register must be written to set 
the flash state machine clock (FCLK). The flash controller module runs at the system clock frequency 
divide by 2, but FCLK must be divided down from this frequency to a frequency between 150 kHz and 
200 kHz. Use the following procedure to set the PRDIV8 and DIV[5:0] bits in the clock configuration 
register.

1. If f

SYS

 is greater than 25.6 MHz, PRDIV8 = 1; otherwise PRDIV8 = 0.

2. Determine DIV[5:0] by using the following equation. Keep only the integer portion of the result 

and discard any fraction. Do not round the result.

3. Therefore, the flash state machine clock is:

Therefore, for Fsys equaling 66 MHz, writing 0x54 to the clock configuration register sets Fclk to 196.43 
kHz, which is a valid frequency for the timing of program and erase operations.

For proper program and erase operations, it is critical to set Fclk between 150 kHz and 200 kHz. Array 
damage due to overstress can occur when Fclk is less than 150 kHz. Incomplete programming and erasure 
can occur when Fclk is greater than 200 kHz.

DIV

Fsys

2x200kHzx 1

PRDIV8x7

(

)

+

(

)

-------------------------------------------------------------------------------

=

Fclk

Fsys

2x DIV

1

+

(

)x 1

PRDIV8x7

(

)

+

(

)

------------------------------------------------------------------------------------

=