Fujitsu MB91191 Manual Do Utilizador
112
CHAPTER 4 External Bus Interface
4.7
Bus Timing
The detailed bus access operation in each mode is shown.
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Time Division I/O Interface
In area 1, time division input/output interface for addresses/data is supported. The time division I/O is
performed the bus width specified by the BW1 and BW0.
performed the bus width specified by the BW1 and BW0.
For the time division input/output interface, a total of four clocks cycle, namely address output cycle (2
clocks) + data access cycle (2 clocks) comprises the basic bus cycle, and for the address output cycle, the
ALE pin is asserted as the output address latch signal.
clocks) + data access cycle (2 clocks) comprises the basic bus cycle, and for the address output cycle, the
ALE pin is asserted as the output address latch signal.
Furthermore, the addresses (A15-A08) indicate the start byte for access to the address pins (A15-A08) in
the same way as normal during the time-shared bus cycle.
the same way as normal during the time-shared bus cycle.
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8 bits bus width read
Figure 4.7-1 8 bits bus width read
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Automatic wait operation at the time division mode (16-bit bus width write)
Figure 4.7-2 Automatic wait operation at the time division mode (16-bit bus width write)
Note:
To access the external extend area, execute dummy read on built-in ROM area prior to access.
AAMD1: MPX=1, BW=00B, WTC=000B, EPCR0:ALEE=1
access --- 8 bit data read
MA1
MA2
BA1
BA2
ACLK
ALE
A15-08
ALE
A15-08
ddr15-08
D31-24
#0
ddr07-00
ddr15-08
ddr07-00
ddr07-00
External RD
At 8-bit bus width, A07 to A00 addresses output to D31 to D24.
CASE
: Read data
Fetch timing
CLK
AMD1: MPX=1, BW=01B, WTC=001B, EPCR0:ALEE=1
aaccess --- 16 bit data write
External
CASE
WR0, WR1
#0:1
MA1
MA2
BA1
BA1
BA2
ACLK
ALE
A15-08
ALE
A15-08
ddr15-08
D31-16
ddr15-00
ddr15-08
ddr15-00
CLK