Samsung S3C8245 Manual Do Utilizador
CONTROL REGISTERS
S3C8245/P8245/C8249/P8249
4-44
TACON
— Timer A Control Register
EDH
Set 1, Bank 0
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
nRESET Value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.6
Timer A Input Clock Selection Bits
0
0
fxx/1024
0
1
fxx/256
1
0
fxx/64
1
1
External clock (TACLK)
.5–.4
Timer A Operating Mode Selection Bits
0
0
Internal mode (TAOUT mode)
0
1
Capture mode (capture on rising edge, counter running, OVF can occur)
1
0
Capture mode (capture on falling edge, counter running, OVF can occur)
1
1
PWM mode (OVF interrupt can occur)
.3
Timer A Counter Clear Bit
0
No effect
1
Clear the timer A counter (when write)
.2
Timer A Overflow Interrupt Enable Bit
0
Disable overflow interrupt
1
Enable overflow interrupt
.1
Timer A Match/Capture Interrupt Enable Bit
0
Disable interrupt
1
Enable interrupt
.0
Timer A Match/Capture Interrupt Pending Bit
0
No interrupt pending
0
Clear pending bit (write)
1
Interrupt is pending