Manual Do Utilizadoríndice analíticoFeatures11. Pin Configurations32. Overview32.1 Block Diagram42.2 Pin Descriptions52.2.1 VCC52.2.2 GND52.2.3 Port B (PB7..PB0)52.2.4 Port C (PC7,PC6)52.2.5 Port D (PD7..PD0)62.2.6 Port E (PE6,PE2)62.2.7 Port F (PF7..PF4, PF1,PF0)62.2.8 D-62.2.9 D+62.2.10 UGND62.2.11 UVCC72.2.12 UCAP72.2.13 VBUS72.2.14 RESET72.2.15 XTAL172.2.16 XTAL272.2.17 AVCC72.2.18 AREF73. About83.1 Disclaimer83.2 Resources83.3 Code Examples83.4 Data Retention84. Register Summary9Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.122. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.123. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instr...124. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega16U4/ATmega32U4 is a complex micro...125. Instruction Set Summary136. Ordering Information166.1 ATmega16U4166.2 ATmega32U4177. Packaging Information187.1 TQFP44187.2 QFN44198. Errata208.1 ATmega16U4/ATmega32U4 Rev E208.2 ATmega16U4/ATmega32U4 Rev D208.3 ATmega16U4/ATmega32U4 Rev C218.4 ATmega16U4/ATmega32U4 Rev B218.5 ATmega16U4/ATmega32U4 Rev A229. Datasheet Revision History for ATmega16U4/ATmega32U4249.1 Rev. 7766F – 11/10249.2 Rev. 7766E – 04/10249.3 Rev. 7766D – 01/09249.4 Rev. 7766C – 11/08249.5 Rev. 7766B – 11/08259.6 Rev. 7766A – 07/0825Tamanho: 600 KBPáginas: 26Language: EnglishAbrir o manual