Manuais de utilizador para Cypress CY7C65113C

índice analítico

• 1.0 Features

  5
• 2.0 Functional Overview

  6
• 3.0 Pin Configurations

  8
• 4.0 Product Summary Tables

  8
  • 4.1 Pin Assignments

    8
  • 4.2 I/O Register Summary

    9
  • 4.3 Instruction Set Summary

    10
• 5.0 Programming Model

  11
  • 5.1 14-bit Program Counter

    11
    • 5.1.1 Program Memory Organization

      12
  • 5.2 8-bit Accumulator (A)

    13
  • 5.3 8-bit Temporary Register (X)

    13
  • 5.4 8-bit Program Stack Pointer (PSP)

    13
    • 5.4.1 Data Memory Organization

      13
  • 5.5 8-bit Data Stack Pointer (DSP)

    14
  • 5.6 Address Modes

    14
    • 5.6.1 Data (Immediate)

      14
    • 5.6.2 Direct

      14
    • 5.6.3 Indexed

      14
• 6.0 Clocking

  15
• 7.0 Reset

  15
  • 7.1 Power-on Reset

    15
  • 7.2 Watchdog Reset

    16
• 8.0 Suspend Mode

  16
• 9.0 General-purpose I/O Ports

  17
  • 9.1 GPIO Configuration Port

    18
  • 9.2 GPIO Interrupt Enable Ports

    19
• 10.0 12-bit Free-Running Timer

  19
• 11.0 I2C Configuration Register

  20
• 12.0 I2C-compatible Controller

  21
• 13.0 Processor Status and Control Register

  23
• 14.0 Interrupts

  24
  • 14.1 Interrupt Vectors

    25
  • 14.2 Interrupt Latency

    26
  • 14.3 USB Bus Reset Interrupt

    26
  • 14.4 Timer Interrupt

    26
  • 14.5 USB Endpoint Interrupts

    27
  • 14.6 USB Hub Interrupt

    27
  • 14.7 GPIO Interrupt

    27
  • 14.8 I2C Interrupt

    27
• 15.0 USB Overview

  28
  • 15.1 USB Serial Interface Engine (SIE)

    28
  • 15.2 USB Enumeration

    28
• 16.0 USB Hub

  29
  • 16.1 Connecting/Disconnecting a USB Device

    29
  • 16.2 Enabling/Disabling a USB Device

    30
  • 16.3 Hub Downstream Ports Status and Control

    30
  • 16.4 Downstream Port Suspend and Resume

    32
  • 16.5 USB Upstream Port Status and Control

    33
• 17.0 USB Serial Interface Engine Operation

  34
  • 17.1 USB Device Addresses

    34
  • 17.2 USB Device Endpoints

    34
  • 17.3 USB Control Endpoint Mode Registers

    35
  • 17.4 USB Non-control Endpoint Mode Registers

    36
  • 17.5 USB Endpoint Counter Registers

    36
  • 17.6 Endpoint Mode/Count Registers Update and Locking Mechanism

    37
• 18.0 USB Mode Tables

  39
• 19.0 Register Summary

  43
• 20.0 Sample Schematic

  45
• 21.0 Absolute Maximum Ratings

  45
• 22.0 Electrical Characteristics

  46
• 23.0 Switching Characteristics (fOSC = 6.0 MHz)

  47
• 24.0 Ordering Information

  48
• 25.0 Package Diagram

  48