Manuais de utilizador para Freescale Semiconductor Block Guide

índice analítico

• Revision History

  2
• Table of Contents

  3
• List of Figures

  5
• List of Tables

  7
• Section 1 Introduction

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  • 1.1 Overview

    11
    • 1.1.1 Glossary

      11
  • 1.2 Features

    11
  • 1.3 Modes of Operation

    11
  • 1.4 Block Diagram

    12
    • Figure 1-1 Module Block Diagram

      12
• Section 2 External Signal Description

  13
  • 2.1 Overview

    13
• Section 3 Memory Map and Registers

  14
  • 3.1 Overview

    14
  • 3.2 Module Memory Map

    14
    • Table 3-1 EEPROM Configuration Field

      14
    • Figure 3-1 EEPROM Memory Map

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    • Table 3-2 EEPROM Register Map

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  • 3.3 Register Descriptions

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    • 3.3.1 ECLKDIV — EEPROM Clock Divider Register

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    • Figure 3-2 EEPROM Clock Divider Register (ECLKDIV)

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    • 3.3.2 RESERVED1

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    • Figure 3-3 RESERVED1

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    • 3.3.3 RESERVED2

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    • Figure 3-4 RESERVED2

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    • 3.3.4 ECNFG — EEPROM Configuration Register

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    • Figure 3-5 EEPROM Configuration Register (ECNFG)

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    • 3.3.5 EPROT — EEPROM Protection Register

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    • Figure 3-6 EEPROM Protection Register (EPROT)

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    • Table 3-3 EEPROM Protection Address Range

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    • 3.3.6 ESTAT — EEPROM Status Register

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    • Figure 3-7 EEPROM Status Register (ESTAT)

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    • 3.3.7 ECMD — EEPROM Command Register

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    • Figure 3-8 EEPROM Command Register (ECMD)

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    • Table 3-4 Valid EEPROM Command List

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    • 3.3.8 RESERVED3

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    • Figure 3-9 RESERVED3

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    • 3.3.9 EADDR — EEPROM Address Registers

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    • Figure 3-10 EEPROM Address High Register (EADDRHI)

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    • Figure 3-11 EEPROM Address Low Register (EADDRLO)

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    • 3.3.10 EDATA — EEPROM Data Registers

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    • Figure 3-12 EEPROM Data High Register (EDATAHI)

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    • Figure 3-13 EEPROM Data Low Register (EDATALO)

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• Section 4 Functional Description

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  • 4.1 EEPROM Command Operations

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    • 4.1.1 Writing the ECLKDIV Register

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    • Figure 4-1 Determination Procedure for PRDIV8 and EDIV Bits

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    • 4.1.2 Command Write Sequence

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    • 4.1.3 EEPROM Commands

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    • Table 4-1 EEPROM Command Description

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    • Figure 4-2 Example Erase Verify Command Flow

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    • Figure 4-3 Example Program Command Flow

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    • Figure 4-4 Example Sector Erase Command Flow

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    • Figure 4-5 Example Mass Erase Command Flow

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    • Figure 4-6 Example Sector Erase Abort Command Flow

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    • Figure 4-7 Example Sector Modify Command Flow

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    • 4.1.4 Illegal EEPROM Operations

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  • 4.2 Wait Mode

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  • 4.3 Stop Mode

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  • 4.4 Background Debug Mode

    40
  • 4.5 EEPROM Module Security

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    • 4.5.1 Unsecuring the MCU in Special Single Chip Mode via the BDM

      40
  • 4.6 Resets

    41
    • 4.6.1 EEPROM Reset Sequence

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    • 4.6.2 Reset While EEPROM Command Active

      41
  • 4.7 Interrupts

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    • Table 4-2 EEPROM Interrupt Sources

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    • 4.7.1 Description of EEPROM Interrupt Operation

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    • Figure 4-8 EEPROM Interrupt Implementation

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• Index

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• Block Guide End Sheet

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