Manual Do Utilizador (DEMO9S08DZ60)índice analíticoCAUTIONARY NOTES4TERMINOLOGY4FEATURES5REFERENCES6GETTING STARTED6OPERATING MODES6RUN MODE6Debug Mode7MEMORY MAP7SOFTWARE DEVELOPMENT8DEVELOPMENT SUPPORT8Integrated BDM8BDM_PORT Header9POWER9POWER SELECT9PWR_SEL9VX_EN10RESET SWITCH10LOW VOLTAGE RESET11TIMING11COMMUNICATIONS11RS-23211COM Connector12LIN Communications12LIN_EN12CAN Communications13CAN Termination13VRH/VRL13USER I/O14POT14SWITCHES14LED’s14User Signals14User Enable15MCU I/O PORT15Tamanho: 100 KBPáginas: 16Language: EnglishAbrir o manual
Ficha De Dados (DEMO9S08DZ60)índice analíticoChapter 1 Device Overview211.1 Devices in the MC9S08DZ60 Series211.2 MCU Block Diagram221.3 System Clock Distribution24Chapter 2 Pins and Connections272.1 Device Pin Assignment272.2 Recommended System Connections302.2.1 Power312.2.2 Oscillator312.2.3 RESET312.2.4 Background / Mode Select (BKGD/MS)322.2.5 ADC Reference Pins (VREFH, VREFL)322.2.6 General-Purpose I/O and Peripheral Ports32Chapter 3 Modes of Operation353.1 Introduction353.2 Features353.3 Run Mode353.4 Active Background Mode353.5 Wait Mode363.6 Stop Modes373.6.1 Stop3 Mode373.6.1.1 LVD Enabled in Stop3 Mode373.6.1.2 Active BDM Enabled in Stop3 Mode383.6.2 Stop2 Mode383.6.3 On-Chip Peripheral Modules in Stop Modes39Chapter 4 Memory414.1 MC9S08DZ60 Series Memory Map414.2 Reset and Interrupt Vector Assignments424.3 Register Addresses and Bit Assignments444.4 RAM524.5 Flash and EEPROM524.5.1 Features524.5.2 Program and Erase Times534.5.3 Program and Erase Command Execution534.5.4 Burst Program Execution554.5.5 Sector Erase Abort574.5.6 Access Errors584.5.7 Block Protection594.5.8 Vector Redirection594.5.9 Security594.5.10 EEPROM Mapping614.5.11 Flash and EEPROM Registers and Control Bits614.5.11.1 Flash and EEPROM Clock Divider Register (FCDIV)614.5.11.2 Flash and EEPROM Options Register (FOPT and NVOPT)624.5.11.3 Flash and EEPROM Configuration Register (FCNFG)644.5.11.4 Flash and EEPROM Protection Register (FPROT and NVPROT)644.5.11.5 Flash and EEPROM Status Register (FSTAT)664.5.11.6 Flash and EEPROM Command Register (FCMD)67Chapter 5 Resets, Interrupts, and General System Control695.1 Introduction695.2 Features695.3 MCU Reset695.4 Computer Operating Properly (COP) Watchdog705.5 Interrupts715.5.1 Interrupt Stack Frame725.5.2 External Interrupt Request (IRQ) Pin725.5.2.1 Pin Configuration Options725.5.2.2 Edge and Level Sensitivity735.5.3 Interrupt Vectors, Sources, and Local Masks735.6 Low-Voltage Detect (LVD) System755.6.1 Power-On Reset Operation755.6.2 Low-Voltage Detection (LVD) Reset Operation755.6.3 Low-Voltage Warning (LVW) Interrupt Operation755.7 MCLK Output755.8 Reset, Interrupt, and System Control Registers and Control Bits765.8.1 Interrupt Pin Request Status and Control Register (IRQSC)775.8.2 System Reset Status Register (SRS)785.8.3 System Background Debug Force Reset Register (SBDFR)795.8.4 System Options Register 1 (SOPT1)805.8.5 System Options Register 2 (SOPT2)815.8.6 System Device Identification Register (SDIDH, SDIDL)825.8.7 System Power Management Status and Control 1 Register (SPMSC1)835.8.8 System Power Management Status and Control 2 Register (SPMSC2)84Chapter 6 Parallel Input/Output Control856.1 Port Data and Data Direction856.2 Pull-up, Slew Rate, and Drive Strength866.3 Pin Interrupts876.3.1 Edge Only Sensitivity876.3.2 Edge and Level Sensitivity886.3.3 Pull-up/Pull-down Resistors886.3.4 Pin Interrupt Initialization886.4 Pin Behavior in Stop Modes886.5 Parallel I/O and Pin Control Registers896.5.1 Port A Registers906.5.1.1 Port A Data Register (PTAD)906.5.1.2 Port A Data Direction Register (PTADD)906.5.1.3 Port A Pull Enable Register (PTAPE)916.5.1.4 Port A Slew Rate Enable Register (PTASE)916.5.1.5 Port A Drive Strength Selection Register (PTADS)926.5.1.6 Port A Interrupt Status and Control Register (PTASC)926.5.1.7 Port A Interrupt Pin Select Register (PTAPS)936.5.1.8 Port A Interrupt Edge Select Register (PTAES)936.5.2 Port B Registers946.5.2.1 Port B Data Register (PTBD)946.5.2.2 Port B Data Direction Register (PTBDD)946.5.2.3 Port B Pull Enable Register (PTBPE)956.5.2.4 Port B Slew Rate Enable Register (PTBSE)956.5.2.5 Port B Drive Strength Selection Register (PTBDS)966.5.2.6 Port B Interrupt Status and Control Register (PTBSC)966.5.2.7 Port B Interrupt Pin Select Register (PTBPS)976.5.2.8 Port B Interrupt Edge Select Register (PTBES)976.5.3 Port C Registers986.5.3.1 Port C Data Register (PTCD)986.5.3.2 Port C Data Direction Register (PTCDD)986.5.3.3 Port C Pull Enable Register (PTCPE)996.5.3.4 Port C Slew Rate Enable Register (PTCSE)996.5.3.5 Port C Drive Strength Selection Register (PTCDS)1006.5.4 Port D Registers1016.5.4.1 Port D Data Register (PTDD)1016.5.4.2 Port D Data Direction Register (PTDDD)1016.5.4.3 Port D Pull Enable Register (PTDPE)1026.5.4.4 Port D Slew Rate Enable Register (PTDSE)1026.5.4.5 Port D Drive Strength Selection Register (PTDDS)1036.5.4.6 Port D Interrupt Status and Control Register (PTDSC)1036.5.4.7 Port D Interrupt Pin Select Register (PTDPS)1046.5.4.8 Port D Interrupt Edge Select Register (PTDES)1046.5.5 Port E Registers1056.5.5.1 Port E Data Register (PTED)1056.5.5.2 Port E Data Direction Register (PTEDD)1056.5.5.3 Port E Pull Enable Register (PTEPE)1066.5.5.4 Port E Slew Rate Enable Register (PTESE)1066.5.5.5 Port E Drive Strength Selection Register (PTEDS)1076.5.6 Port F Registers1086.5.6.1 Port F Data Register (PTFD)1086.5.6.2 Port F Data Direction Register (PTFDD)1086.5.6.3 Port F Pull Enable Register (PTFPE)1096.5.6.4 Port F Slew Rate Enable Register (PTFSE)1096.5.6.5 Port F Drive Strength Selection Register (PTFDS)1106.5.7 Port G Registers1116.5.7.1 Port G Data Register (PTGD)1116.5.7.2 Port G Data Direction Register (PTGDD)1116.5.7.3 Port G Pull Enable Register (PTGPE)1126.5.7.4 Port G Slew Rate Enable Register (PTGSE)1126.5.7.5 Port G Drive Strength Selection Register (PTGDS)113Chapter 7 Central Processor Unit (S08CPUV3)1157.1 Introduction1157.1.1 Features1157.2 Programmer’s Model and CPU Registers1167.2.1 Accumulator (A)1167.2.2 Index Register (H:X)1167.2.3 Stack Pointer (SP)1177.2.4 Program Counter (PC)1177.2.5 Condition Code Register (CCR)1177.3 Addressing Modes1197.3.1 Inherent Addressing Mode (INH)1197.3.2 Relative Addressing Mode (REL)1197.3.3 Immediate Addressing Mode (IMM)1197.3.4 Direct Addressing Mode (DIR)1197.3.5 Extended Addressing Mode (EXT)1207.3.6 Indexed Addressing Mode1207.3.6.1 Indexed, No Offset (IX)1207.3.6.2 Indexed, No Offset with Post Increment (IX+)1207.3.6.3 Indexed, 8-Bit Offset (IX1)1207.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+)1207.3.6.5 Indexed, 16-Bit Offset (IX2)1207.3.6.6 SP-Relative, 8-Bit Offset (SP1)1207.3.6.7 SP-Relative, 16-Bit Offset (SP2)1217.4 Special Operations1217.4.1 Reset Sequence1217.4.2 Interrupt Sequence1217.4.3 Wait Mode Operation1227.4.4 Stop Mode Operation1227.4.5 BGND Instruction1237.5 HCS08 Instruction Set Summary124Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)1358.1 Introduction1358.1.1 Features1378.1.2 Modes of Operation1398.2 External Signal Description1398.3 Register Definition1408.3.1 MCG Control Register 1 (MCGC1)1408.3.2 MCG Control Register 2 (MCGC2)1418.3.3 MCG Trim Register (MCGTRM)1428.3.4 MCG Status and Control Register (MCGSC)1438.3.5 MCG Control Register 3 (MCGC3)1448.4 Functional Description1468.4.1 Operational Modes1468.4.1.1 FLL Engaged Internal (FEI)1478.4.1.2 FLL Engaged External (FEE)1478.4.1.3 FLL Bypassed Internal (FBI)1478.4.1.4 FLL Bypassed External (FBE)1488.4.1.5 PLL Engaged External (PEE)1488.4.1.6 PLL Bypassed External (PBE)1498.4.1.7 Bypassed Low Power Internal (BLPI)1498.4.1.8 Bypassed Low Power External (BLPE)1498.4.1.9 Stop1508.4.2 Mode Switching1508.4.3 Bus Frequency Divider1518.4.4 Low Power Bit Usage1518.4.5 Internal Reference Clock1518.4.6 External Reference Clock1518.4.7 Fixed Frequency Clock1528.5 Initialization / Application Information1528.5.1 MCG Module Initialization Sequence1528.5.1.1 Initializing the MCG1528.5.2 MCG Mode Switching1538.5.2.1 Example # 1: Moving from FEI to PEE Mode: External Crystal = 4 MHz, Bus Frequency = 8 MHz1548.5.2.2 Example # 2: Moving from PEE to BLPI Mode: External Crystal = 4 MHz, Bus Frequency =16 kHz1578.5.2.3 Example #3: Moving from BLPI to FEE Mode: External Crystal = 4 MHz, Bus Frequency = 16 MHz1598.5.2.4 Example # 4: Moving from FEI to PEE Mode: External Crystal = 8 MHz, Bus Frequency = 8 MHz1608.5.3 Calibrating the Internal Reference Clock (IRC)1648.5.3.1 Example #5: Internal Reference Clock Trim164Chapter 9 Analog Comparator (S08ACMPV3)1679.1 Introduction1679.1.1 ACMP Configuration Information1679.1.2 Features1699.1.3 Modes of Operation1699.1.3.1 ACMP in Wait Mode1699.1.3.2 ACMP in Stop Modes1699.1.3.3 ACMP in Active Background Mode1699.1.4 Block Diagram1709.2 External Signal Description1709.3 Memory Map/Register Definition1719.3.1 ACMPx Status and Control Register (ACMPxSC)1719.4 Functional Description172Chapter 10 Analog-to-Digital Converter (S08ADC12V1)17310.1 Introduction17310.1.1 Analog Power and Ground Signal Names17310.1.2 Channel Assignments17310.1.3 Alternate Clock17410.1.4 Hardware Trigger17410.1.5 Temperature Sensor17510.1.6 Features17710.1.7 ADC Module Block Diagram17710.2 External Signal Description17810.2.1 Analog Power (VDDAD)17910.2.2 Analog Ground (VSSAD)17910.2.3 Voltage Reference High (VREFH)17910.2.4 Voltage Reference Low (VREFL)17910.2.5 Analog Channel Inputs (ADx)17910.3 Register Definition17910.3.1 Status and Control Register 1 (ADCSC1)17910.3.2 Status and Control Register 2 (ADCSC2)18110.3.3 Data Result High Register (ADCRH)18110.3.4 Data Result Low Register (ADCRL)18210.3.5 Compare Value High Register (ADCCVH)18210.3.6 Compare Value Low Register (ADCCVL)18310.3.7 Configuration Register (ADCCFG)18310.3.8 Pin Control 1 Register (APCTL1)18410.3.9 Pin Control 2 Register (APCTL2)18510.3.10 Pin Control 3 Register (APCTL3)18610.4 Functional Description18710.4.1 Clock Select and Divide Control18810.4.2 Input Select and Pin Control18810.4.3 Hardware Trigger18810.4.4 Conversion Control18810.4.4.1 Initiating Conversions18910.4.4.2 Completing Conversions18910.4.4.3 Aborting Conversions18910.4.4.4 Power Control19010.4.4.5 Sample Time and Total Conversion Time19010.4.5 Automatic Compare Function19110.4.6 MCU Wait Mode Operation19110.4.7 MCU Stop3 Mode Operation19210.4.7.1 Stop3 Mode With ADACK Disabled19210.4.7.2 Stop3 Mode With ADACK Enabled19210.4.8 MCU Stop2 Mode Operation19210.5 Initialization Information19310.5.1 ADC Module Initialization Example19310.5.1.1 Initialization Sequence19310.5.1.2 Pseudo-Code Example19310.6 Application Information19510.6.1 External Pins and Routing19510.6.1.1 Analog Supply Pins19510.6.1.2 Analog Reference Pins19510.6.1.3 Analog Input Pins19610.6.2 Sources of Error19610.6.2.1 Sampling Error19610.6.2.2 Pin Leakage Error19610.6.2.3 Noise-Induced Errors19710.6.2.4 Code Width and Quantization Error19710.6.2.5 Linearity Errors19810.6.2.6 Code Jitter, Non-Monotonicity, and Missing Codes198Chapter 11 Inter-Integrated Circuit (S08IICV2)19911.1 Introduction19911.2 External Signal Description20211.3 Register Definition20211.4 Functional Description20911.5 Resets21411.6 Interrupts21411.7 Initialization/Application Information216Chapter 12 Freescale Controller Area Network (S08MSCANV1)21912.1 Introduction21912.1.1 Features22112.1.2 Modes of Operation22112.1.3 Block Diagram22212.2 External Signal Description22212.2.1 RXCAN - CAN Receiver Input Pin22212.2.2 TXCAN - CAN Transmitter Output Pin22212.2.3 CAN System22212.3 Register Definition22312.3.1 MSCAN Control Register 0 (CANCTL0)22312.3.2 MSCAN Control Register 1 (CANCTL1)22612.3.3 MSCAN Bus Timing Register 0 (CANBTR0)22712.3.4 MSCAN Bus Timing Register 1 (CANBTR1)22812.3.4.1 MSCAN Receiver Flag Register (CANRFLG)22912.3.5 MSCAN Receiver Interrupt Enable Register (CANRIER)23112.3.6 MSCAN Transmitter Flag Register (CANTFLG)23212.3.7 MSCAN Transmitter Interrupt Enable Register (CANTIER)23312.3.8 MSCAN Transmitter Message Abort Request Register (CANTARQ)23412.3.9 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)23512.3.10 MSCAN Transmit Buffer Selection Register (CANTBSEL)23512.3.11 MSCAN Identifier Acceptance Control Register (CANIDAC)23612.3.12 MSCAN Miscellaneous Register (CANMISC)23712.3.13 MSCAN Receive Error Counter (CANRXERR)23812.3.14 MSCAN Transmit Error Counter (CANTXERR)23912.3.15 MSCAN Identifier Acceptance Registers (CANIDAR0-7)23912.3.16 MSCAN Identifier Mask Registers (CANIDMR0-CANIDMR7)24012.4 Programmer’s Model of Message Storage24112.4.1 Identifier Registers (IDR0-IDR3)24412.4.1.1 IDR0-IDR3 for Extended Identifier Mapping24412.4.2 IDR0-IDR3 for Standard Identifier Mapping24612.4.3 Data Segment Registers (DSR0-7)24712.4.4 Data Length Register (DLR)24812.4.5 Transmit Buffer Priority Register (TBPR)24912.4.6 Time Stamp Register (TSRH-TSRL)24912.5 Functional Description25012.5.1 General25012.5.2 Message Storage25112.5.2.1 Message Transmit Background25212.5.2.2 Transmit Structures25212.5.2.3 Receive Structures25312.5.3 Identifier Acceptance Filter25412.5.3.1 Identifier Acceptance Filters example25812.5.3.2 Protocol Violation Protection25912.5.3.3 Clock System25912.5.4 Modes of Operation26112.5.4.1 Normal Modes26112.5.4.2 Special Modes26112.5.4.3 Emulation Modes26212.5.4.4 Listen-Only Mode26212.5.4.5 Security Modes26212.5.4.6 Loopback Self Test Mode26212.5.5 Low-Power Options26212.5.5.1 Operation in Run Mode26312.5.5.2 Operation in Wait Mode26312.5.5.3 Operation in Stop Mode26312.5.5.4 MSCAN Sleep Mode26412.5.5.5 MSCAN Initialization Mode26712.5.5.6 MSCAN Power Down Mode26812.5.5.7 Programmable Wake-Up Function26812.5.6 Reset Initialization26812.5.7 Interrupts26812.5.7.1 Description of Interrupt Operation26912.5.7.2 Transmit Interrupt26912.5.7.3 Receive Interrupt26912.5.7.4 Wake-Up Interrupt26912.5.7.5 Error Interrupt26912.5.7.6 Interrupt Acknowledge27012.5.7.7 Recovery from Stop or Wait27012.6 Initialization/Application Information27012.6.1 MSCAN initialization27012.6.2 Bus-Off Recovery271Chapter 13 Serial Peripheral Interface (S08SPIV3)27313.1 Introduction27313.1.1 Features27513.1.2 Block Diagrams27513.1.2.1 SPI System Block Diagram27513.1.2.2 SPI Module Block Diagram27613.1.3 SPI Baud Rate Generation27713.2 External Signal Description27813.2.1 SPSCK - SPI Serial Clock27813.2.2 MOSI - Master Data Out, Slave Data In27813.2.3 MISO - Master Data In, Slave Data Out27813.2.4 SS - Slave Select27813.3 Modes of Operation27913.3.1 SPI in Stop Modes27913.4 Register Definition27913.4.1 SPI Control Register 1 (SPIC1)27913.4.2 SPI Control Register 2 (SPIC2)28013.4.3 SPI Baud Rate Register (SPIBR)28113.4.4 SPI Status Register (SPIS)28213.4.5 SPI Data Register (SPID)28313.5 Functional Description28413.5.1 SPI Clock Formats28413.5.2 SPI Interrupts28713.5.3 Mode Fault Detection287Chapter 14 Serial Communications Interface (S08SCIV4)28914.1 Introduction28914.1.1 SCI2 Configuration Information28914.1.2 Features29114.1.3 Modes of Operation29114.1.4 Block Diagram29214.2 Register Definition29414.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL)29414.2.2 SCI Control Register 1 (SCIxC1)29514.2.3 SCI Control Register 2 (SCIxC2)29614.2.4 SCI Status Register 1 (SCIxS1)29714.2.5 SCI Status Register 2 (SCIxS2)29914.2.6 SCI Control Register 3 (SCIxC3)30014.2.7 SCI Data Register (SCIxD)30114.3 Functional Description30114.3.1 Baud Rate Generation30114.3.2 Transmitter Functional Description30214.3.2.1 Send Break and Queued Idle30314.3.3 Receiver Functional Description30314.3.3.1 Data Sampling Technique30414.3.3.2 Receiver Wakeup Operation30414.3.4 Interrupts and Status Flags30514.3.5 Additional SCI Functions30614.3.5.1 8- and 9-Bit Data Modes30614.3.5.2 Stop Mode Operation30714.3.5.3 Loop Mode30714.3.5.4 Single-Wire Operation307Chapter 15 Real-Time Counter (S08RTCV1)30915.1 Introduction30915.1.1 RTC Clock Signal Names30915.1.2 Features31115.1.3 Modes of Operation31115.1.3.1 Wait Mode31115.1.3.2 Stop Modes31115.1.3.3 Active Background Mode31115.1.4 Block Diagram31215.2 External Signal Description31215.3 Register Definition31215.3.1 RTC Status and Control Register (RTCSC)31315.3.2 RTC Counter Register (RTCCNT)31415.3.3 RTC Modulo Register (RTCMOD)31415.4 Functional Description31415.4.1 RTC Operation Example31515.5 Initialization/Application Information316Chapter 16 Timer Pulse-Width Modulator (S08TPMV3)31916.1 Introduction31916.1.1 Features32116.1.2 Modes of Operation32116.1.3 Block Diagram32216.2 Signal Description32416.2.1 Detailed Signal Descriptions32416.2.1.1 EXTCLK - External Clock Source32516.2.1.2 TPMxCHn - TPM Channel n I/O Pin(s)32516.3 Register Definition32816.3.1 TPM Status and Control Register (TPMxSC)32816.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL)32916.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL)33016.3.4 TPM Channel n Status and Control Register (TPMxCnSC)33116.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL)33316.4 Functional Description33416.4.1 Counter33516.4.1.1 Counter Clock Source33516.4.1.2 Counter Overflow and Modulo Reset33616.4.1.3 Counting Modes33716.4.1.4 Manual Counter Reset33716.4.2 Channel Mode Selection33716.4.2.1 Input Capture Mode33716.4.2.2 Output Compare Mode33716.4.2.3 Edge-Aligned PWM Mode33816.4.2.4 Center-Aligned PWM Mode33916.5 Reset Overview34016.5.1 General34016.5.2 Description of Reset Operation34016.6 Interrupts34016.6.1 General34016.6.2 Description of Interrupt Operation34116.6.2.1 Timer Overflow Interrupt (TOF) Description34116.6.2.1.1 Normal Case34116.6.2.1.2 Center-Aligned PWM Case34216.6.2.2 Channel Event Interrupt Description34216.6.2.2.1 Input Capture Events34216.6.2.2.2 Output Compare Events34216.6.2.2.3 PWM End-of-Duty-Cycle Events34216.7 The Differences from TPM v2 to TPM v3342Chapter 17 Development Support34717.1 Introduction34717.1.1 Forcing Active Background34717.1.2 Features34817.2 Background Debug Controller (BDC)34817.2.1 BKGD Pin Description34917.2.2 Communication Details35017.2.3 BDC Commands35417.2.4 BDC Hardware Breakpoint35617.3 On-Chip Debug System (DBG)35717.3.1 Comparators A and B35717.3.2 Bus Capture Information and FIFO Operation35717.3.3 Change-of-Flow Information35817.3.4 Tag vs. Force Breakpoints and Triggers35817.3.5 Trigger Modes35917.3.6 Hardware Breakpoints36117.4 Register Definition36117.4.1 BDC Registers and Control Bits36117.4.1.1 BDC Status and Control Register (BDCSCR)36217.4.1.2 BDC Breakpoint Match Register (BDCBKPT)36317.4.2 System Background Debug Force Reset Register (SBDFR)36317.4.3 DBG Registers and Control Bits36417.4.3.1 Debug Comparator A High Register (DBGCAH)36417.4.3.2 Debug Comparator A Low Register (DBGCAL)36417.4.3.3 Debug Comparator B High Register (DBGCBH)36417.4.3.4 Debug Comparator B Low Register (DBGCBL)36417.4.3.5 Debug FIFO High Register (DBGFH)36517.4.3.6 Debug FIFO Low Register (DBGFL)36517.4.3.7 Debug Control Register (DBGC)36617.4.3.8 Debug Trigger Register (DBGT)36717.4.3.9 Debug Status Register (DBGS)368Appendix A Electrical Characteristics369A.1 Introduction369A.2 Parameter Classification369A.3 Absolute Maximum Ratings369A.4 Thermal Characteristics370A.5 ESD Protection and Latch-Up Immunity372A.6 DC Characteristics373A.7 Supply Current Characteristics375A.8 Analog Comparator (ACMP) Electricals376A.9 ADC Characteristics376A.10 External Oscillator (XOSC) Characteristics380A.11 MCG Specifications381A.12 AC Characteristics383A.12.1 Control Timing383A.12.2 Timer/PWM384A.12.3 MSCAN385A.12.4 SPI386A.13 Flash and EEPROM389A.14 EMC Performance390A.14.1 Radiated Emissions390Appendix B Timer Pulse-Width Modulator (TPMV2)391B.0.1 Features391B.0.2 Block Diagram391B.1 External Signal Description393B.1.1 External TPM Clock Sources393B.1.2 TPMxCHn - TPMx Channel n I/O Pins393B.2 Register Definition393B.2.1 Timer Status and Control Register (TPMxSC)394B.2.2 Timer Counter Registers (TPMxCNTH:TPMxCNTL)395B.2.3 Timer Counter Modulo Registers (TPMxMODH:TPMxMODL)396B.2.4 Timer Channel n Status and Control Register (TPMxCnSC)397B.2.5 Timer Channel Value Registers (TPMxCnVH:TPMxCnVL)398B.3 Functional Description399B.3.1 Counter399B.3.2 Channel Mode Selection400B.3.2.1 Input Capture Mode400B.3.2.2 Output Compare Mode401B.3.2.3 Edge-Aligned PWM Mode401B.3.3 Center-Aligned PWM Mode402B.4 TPM Interrupts403B.4.1 Clearing Timer Interrupt Flags403B.4.2 Timer Overflow Interrupt Description403B.4.3 Channel Event Interrupt Description404B.4.4 PWM End-of-Duty-Cycle Events404Appendix C Ordering Information and Mechanical Drawings405C.1 Ordering Information405C.1.1 MC9S08DZ60 Series Devices405C.2 Mechanical Drawings405Tamanho: 4 MBPáginas: 416Language: EnglishAbrir o manual
