Manuais de utilizador para Freescale Semiconductor Demonstration Board for MC9RS08KA2 von Freescale DEMO9RS08KA2

índice analítico

• Chapter 1 MC9RS08KA2 Series Device Overview

  15
  • 1.1 Overview

    15
  • 1.2 MCU Block Diagram

    15
  • 1.3 System Clock Distribution

    16
• Chapter 2 Pins and Connections

  17
  • 2.1 Introduction

    17
  • 2.2 Device Pin Assignment

    17
  • 2.3 Recommended System Connections

    18
  • 2.4 Pin Detail

    18
    • 2.4.1 Power

      19
    • 2.4.2 PTA2/KBIP2/TCLK/RESET/VPP

      19
    • 2.4.3 PTA3/ACMPO/BKGD/MS

      19
    • 2.4.4 General-Purpose I/O and Peripheral Ports

      20
• Chapter 3 Modes of Operation

  21
  • 3.1 Introduction

    21
  • 3.2 Features

    21
  • 3.3 Run Mode

    21
  • 3.4 Active Background Mode

    21
  • 3.5 Wait Mode

    22
  • 3.6 Stop Mode

    23
    • 3.6.1 Active BDM Enabled in Stop Mode

      24
    • 3.6.2 LVD Enabled in Stop Mode

      24
• Chapter 4 Memory

  25
  • 4.1 Memory Map

    25
  • 4.2 Unimplemented Memory

    27
  • 4.3 Indexed/Indirect Addressing

    27
  • 4.4 RAM and Register Addresses and Bit Assignments

    27
  • 4.5 RAM

    29
  • 4.6 Flash

    29
    • 4.6.1 Features

      29
    • 4.6.2 Flash Programming Procedure

      30
    • 4.6.3 Flash Mass Erase Operation

      30
    • 4.6.4 Security

      31
  • 4.7 Flash Registers and Control Bits

    32
    • 4.7.1 Flash Options Register (FOPT and NVOPT)

      32
    • 4.7.2 Flash Control Register (FLCR)

      33
  • 4.8 Page Select Register (PAGESEL)

    33
• Chapter 5 Resets, Interrupts, and General System Control

  35
  • 5.1 Introduction

    35
  • 5.2 Features

    35
  • 5.3 MCU Reset

    35
  • 5.4 Computer Operating Properly (COP) Watchdog

    36
  • 5.5 Interrupts

    36
  • 5.6 Low-Voltage Detect (LVD) System

    37
    • 5.6.1 Power-On Reset Operation

      37
    • 5.6.2 LVD Reset Operation

      37
    • 5.6.3 LVD Interrupt Operation

      37
  • 5.7 Real-Time Interrupt (RTI)

    37
  • 5.8 Reset, Interrupt, and System Control Registers and Control Bits

    38
    • 5.8.1 System Reset Status Register (SRS)

      38
    • 5.8.2 System Options Register (SOPT)

      39
    • 5.8.3 System Device Identification Register (SDIDH, SDIDL)

      40
    • 5.8.4 System Real-Time Interrupt Status and Control Register (SRTISC)

      41
    • 5.8.5 System Power Management Status and Control 1 Register (SPMSC1)

      43
    • 5.8.6 System Interrupt Pending Register (SIP1)

      44
• Chapter 6 Parallel Input/Output Control

  45
  • 6.1 Pin Behavior in Low-Power Modes

    46
  • 6.2 Parallel I/O Registers

    46
    • 6.2.1 Port A Registers

      46
  • 6.3 Pin Control Registers

    47
    • 6.3.1 Port A Pin Control Registers

      47
      • 6.3.1.1 Internal Pulling Device Enable

        47
      • 6.3.1.2 Pullup/Pulldown Control

        48
      • 6.3.1.3 Output Slew Rate Control Enable

        48
• Chapter 7 Keyboard Interrupt (RS08KBIV1)

  51
  • 7.1 Introduction

    51
    • 7.1.1 Features

      51
    • 7.1.2 Modes of Operation

      52
      • 7.1.2.1 Operation in Wait Mode

        52
      • 7.1.2.2 Operation in Stop Mode

        52
      • 7.1.2.3 Operation in Active Background Mode

        52
    • 7.1.3 Block Diagram

      52
  • 7.2 External Signal Description

    52
  • 7.3 Register Definition

    53
    • 7.3.1 KBI Status and Control Register (KBISC)

      53
    • 7.3.2 KBI Pin Enable Register (KBIPE)

      54
    • 7.3.3 KBI Edge Select Register (KBIES)

      54
  • 7.4 Functional Description

    55
    • 7.4.1 Edge Only Sensitivity

      55
    • 7.4.2 Edge and Level Sensitivity

      55
    • 7.4.3 KBI Pullup/Pulldown Device

      55
    • 7.4.4 KBI Initialization

      55
• Chapter 8 Central Processor Unit (RS08CPUV1)

  57
  • 8.1 Introduction

    57
  • 8.2 Programmer’s Model and CPU Registers

    57
    • 8.2.1 Accumulator (A)

      58
    • 8.2.2 Program Counter (PC)

      59
    • 8.2.3 Shadow Program Counter (SPC)

      59
    • 8.2.4 Condition Code Register (CCR)

      59
    • 8.2.5 Indexed Data Register (D[X])

      60
    • 8.2.6 Index Register (X)

      60
    • 8.2.7 Page Select Register (PAGESEL)

      61
  • 8.3 Addressing Modes

    61
    • 8.3.1 Inherent Addressing Mode (INH)

      61
    • 8.3.2 Relative Addressing Mode (REL)

      61
    • 8.3.3 Immediate Addressing Mode (IMM)

      62
    • 8.3.4 Tiny Addressing Mode (TNY)

      62
    • 8.3.5 Short Addressing Mode (SRT)

      63
    • 8.3.6 Direct Addressing Mode (DIR)

      63
    • 8.3.7 Extended Addressing Mode (EXT)

      63
    • 8.3.8 Indexed Addressing Mode (IX, Implemented by Pseudo Instructions)

      63
  • 8.4 Special Operations

    63
    • 8.4.1 Reset Sequence

      64
    • 8.4.2 Interrupts

      64
    • 8.4.3 Wait and Stop Mode

      64
    • 8.4.4 Active Background Mode

      64
  • 8.5 Summary Instruction Table

    65
• Chapter 9 Internal Clock Source (RS08ICSV1)

  75
  • 9.1 Introduction

    75
    • 9.1.1 Features

      76
    • 9.1.2 Modes of Operation

      76
      • 9.1.2.1 FLL Engaged Internal (FEI)

        76
      • 9.1.2.2 FLL Bypassed Internal (FBI)

        76
      • 9.1.2.3 FLL Bypassed Internal Low Power (FBILP)

        76
      • 9.1.2.4 Stop (STOP)

        76
    • 9.1.3 Block Diagram

      76
  • 9.2 External Signal Description

    77
  • 9.3 Register Definition

    77
    • 9.3.1 ICS Control Register 1 (ICSC1)

      77
    • 9.3.2 ICS Control Register 2 (ICSC2)

      78
    • 9.3.3 ICS Trim Register (ICSTRM)

      79
    • 9.3.4 ICS Status and Control (ICSSC)

      79
  • 9.4 Functional Description

    80
    • 9.4.1 Operational Modes

      80
      • 9.4.1.1 FLL Engaged Internal (FEI)

        80
      • 9.4.1.2 FLL Bypassed Internal (FBI)

        80
      • 9.4.1.3 FLL Bypassed Internal Low Power (FBILP)

        80
      • 9.4.1.4 Stop

        81
    • 9.4.2 Mode Switching

      81
    • 9.4.3 Bus Frequency Divider

      81
    • 9.4.4 Low Power Bit Usage

      81
    • 9.4.5 Internal Reference Clock

      81
    • 9.4.6 Fixed Frequency Clock

      82
• Chapter 10 Analog Comparator (RS08ACMPV1)

  83
  • 10.1 Introduction

    83
    • 10.1.1 Features

      84
    • 10.1.2 Modes of Operation

      84
      • 10.1.2.1 Operation in Wait Mode

        84
      • 10.1.2.2 Operation in Stop Mode

        84
      • 10.1.2.3 Operation in Active Background Mode

        84
    • 10.1.3 Block Diagram

      84
  • 10.2 External Signal Description

    86
  • 10.3 Register Definition

    86
    • 10.3.1 ACMP Status and Control Register (ACMPSC)

      86
  • 10.4 Functional Description

    87
• Chapter 11 Modulo Timer (RS08MTIMV1)

  89
  • 11.1 Introduction

    89
    • 11.1.1 Features

      90
    • 11.1.2 Modes of Operation

      90
      • 11.1.2.1 Operation in Wait Mode

        90
      • 11.1.2.2 Operation in Stop Modes

        90
      • 11.1.2.3 Operation in Active Background Mode

        90
    • 11.1.3 Block Diagram

      91
  • 11.2 External Signal Description

    91
  • 11.3 Register Definition

    91
    • 11.3.1 MTIM Status and Control Register (MTIMSC)

      92
    • 11.3.2 MTIM Clock Configuration Register (MTIMCLK)

      93
    • 11.3.3 MTIM Counter Register (MTIMCNT)

      93
    • 11.3.4 MTIM Modulo Register (MTIMMOD)

      94
  • 11.4 Functional Description

    95
    • 11.4.1 MTIM Operation Example

      96
• Chapter 12 Development Support

  97
  • 12.1 Introduction

    97
  • 12.2 Features

    97
  • 12.3 RS08 Background Debug Controller (BDC)

    98
    • 12.3.1 BKGD Pin Description

      99
    • 12.3.2 Communication Details

      99
    • 12.3.3 SYNC and Serial Communication Timeout

      102
  • 12.4 BDC Registers and Control Bits

    103
    • 12.4.1 BDC Status and Control Register (BDCSCR)

      103
    • 12.4.2 BDC Breakpoint Match Register

      104
  • 12.5 RS08 BDC Commands

    105
• Appendix A Electrical Characteristics

  109
  • A.1 Introduction

    109
  • A.2 Absolute Maximum Ratings

    109
  • A.3 Thermal Characteristics

    110
  • A.4 Electrostatic Discharge (ESD) Protection Characteristics

    111
  • A.5 DC Characteristics

    111
  • A.6 Supply Current Characteristics

    115
  • A.7 Analog Comparator (ACMP) Electricals

    117
  • A.8 Internal Clock Source Characteristics

    117
  • A.9 AC Characteristics

    118
    • A.9.1 Control Timing

      118
  • A.10 FLASH Specifications

    119
• Appendix B Ordering Information and Mechanical Drawings

  123
  • B.1 Ordering Information

    123
  • B.2 Mechanical Drawings

    123