Manuais de utilizador para Fujitsu MB89202

índice analítico

• CHAPTER 1 OVERVIEW

  17
  • 1.1 Features of MB89202/F202RA Series

    18
  • 1.2 MB89202/F202RA Series Product Lineup

    20
  • 1.3 Differences between Models

    22
  • 1.4 Block Diagram of MB89202/F202RA Series

    23
  • 1.5 Pin Assignment

    24
  • 1.6 Package Dimensions

    26
  • 1.7 Pin Functions Description

    28
  • 1.8 I/O Circuit Types

    30
• CHAPTER 2 HANDLING DEVICES

  33
  • 2.1 Precautions on Handling Devices

    34
• CHAPTER 3 CPU

  37
  • 3.1 Memory Space

    38
    • 3.1.1 Specific-purpose Areas

      40
    • 3.1.2 Location of 16-bit Data on Memory

      42
  • 3.2 Dedicated Register

    43
    • 3.2.1 Condition Code Register (CCR)

      45
    • 3.2.2 Register Bank Pointer (RP)

      47
  • 3.3 General-Purpose Registers

    48
  • 3.4 Interrupts

    50
    • 3.4.1 Interrupt Level Setting Registers (ILR1 to ILR4)

      52
    • 3.4.2 Steps in the Interrupt Operation

      53
    • 3.4.3 Multiple Interrupts

      55
    • 3.4.4 Interrupt Processing Time

      56
    • 3.4.5 Stack Operation at Interrupt Processing

      57
    • 3.4.6 Stack Area for Interrupt Processing

      58
  • 3.5 Reset

    59
    • 3.5.1 Reset Flag Register (RSFR)

      61
    • 3.5.2 External Reset Pin

      63
    • 3.5.3 Reset Operation

      64
    • 3.5.4 State of Each Pin at Reset

      66
  • 3.6 Clock

    67
    • 3.6.1 Clock Generator

      69
    • 3.6.2 Clock Controller

      70
    • 3.6.3 System Clock Control Register (SYCC)

      72
    • 3.6.4 Clock Mode

      74
    • 3.6.5 Oscillation Stabilization Wait Time

      76
  • 3.7 Standby Mode (Low-Power Consumption Mode)

    78
    • 3.7.1 Operations in Standby Mode

      79
    • 3.7.2 Sleep Mode

      80
    • 3.7.3 Stop Mode

      81
    • 3.7.4 Standby Control Register (STBC)

      82
    • 3.7.5 Diagram for State Transition in Standby Mode

      84
    • 3.7.6 Notes on Standby Mode

      86
  • 3.8 Memory Access Mode

    88
• CHAPTER 4 I/O PORTS

  91
  • 4.1 Overview of I/O Ports

    92
  • 4.2 Port 0

    94
    • 4.2.1 Registers of Port 0 (PDR0, DDR0, and PUL0)

      96
    • 4.2.2 Operations of Port 0 Functions

      98
  • 4.3 Port 3

    100
    • 4.3.1 Registers of Port 3 (PDR3, DDR3, PUL3)

      102
    • 4.3.2 Operations of Port 3 Functions

      104
  • 4.4 Port 4

    106
    • 4.4.1 Registers of Port 4 (PDR4)

      108
    • 4.4.2 Operations of Port 4 Functions

      109
  • 4.5 Port 5

    110
    • 4.5.1 Registers of Port 5 (PDR5, DDR5, PUL5)

      112
    • 4.5.2 Operations of Port 5 Functions

      114
  • 4.6 Port 6

    116
    • 4.6.1 Registers of Port 6 (PDR6, DDR6, PUL6)

      119
    • 4.6.2 Operations of Port 6 Functions

      121
  • 4.7 Port 7

    123
    • 4.7.1 Registers of Port 7 (PDR7, DDR7, PUL7)

      125
    • 4.7.2 Operations of Port 7 Functions

      127
  • 4.8 Programming Example of I/O Port

    129
• CHAPTER 5 TIME-BASE TIMER

  131
  • 5.1 Overview of Time-base Timer

    132
  • 5.2 Configuration of Time-base Timer

    134
  • 5.3 Time-base Timer Control Register (TBTC)

    135
  • 5.4 Interrupt of Time-base Timer

    137
  • 5.5 Operations of Time-base Timer Functions

    138
  • 5.6 Notes on Using Time-base Timer

    140
  • 5.7 Program Example for Time-base Timer

    141
• CHAPTER 6 WATCHDOG TIMER

  143
  • 6.1 Overview of Watchdog Timer

    144
  • 6.2 Configuration of Watchdog Timer

    145
  • 6.3 Watchdog Control Register (WDTC)

    146
  • 6.4 Operations of Watchdog Timer Functions

    147
  • 6.5 Notes on Using Watchdog Timer

    148
  • 6.6 Program Example for Watchdog Timer

    149
• CHAPTER 7 8-BIT PWM TIMER

  151
  • 7.1 Overview of 8-bit PWM Timer

    152
  • 7.2 Configuration of 8-bit PWM Timer

    155
  • 7.3 Pin of 8-bit PWM Timer

    157
  • 7.4 Registers of 8-bit PWM Timer

    158
    • 7.4.1 PWM Control Register (CNTR)

      159
    • 7.4.2 PWM Compare Register (COMR)

      161
  • 7.5 Interrupt of 8-bit PWM Timer

    163
  • 7.6 Operations of the Interval Timer Functions

    164
  • 7.7 Operations of the 8-bit PWM Timer Functions

    166
  • 7.8 States in Each Mode During Operation

    168
  • 7.9 Notes on Using 8-bit PWM Timer

    171
  • 7.10 Program Example for PWM Timer

    173
• CHAPTER 8 8/16-BIT CAPTURE TIMER/ COUNTER

  177
  • 8.1 Overview of 8/16-bit Capture Timer/Counter

    178
  • 8.2 Configuration of 8/16-bit Capture Timer/Counter

    182
  • 8.3 Pins of 8/16-bit Capture Timer/Counter

    184
  • 8.4 Registers of 8/16-bit Capture Timer/Counter

    186
    • 8.4.1 Capture Control Register (TCCR)

      187
    • 8.4.2 Timer 0 Control Register (TCR0)

      189
    • 8.4.3 Timer 1 Control Register (TCR1)

      191
    • 8.4.4 Timer Output Control Register (TCR2)

      193
    • 8.4.5 Timer 0 Data Register (TDR0)

      194
    • 8.4.6 Timer 1 Data Register (TDR1)

      196
    • 8.4.7 Capture Data Registers H and L (TCPH and TCPL)

      198
  • 8.5 8/16-bit Capture Timer/Counter of Interrupts

    199
  • 8.6 Explanation of Operations of Interval Timer Functions

    201
  • 8.7 Operation of Counter Functions

    205
  • 8.8 Functions of Operations of Capture Functions

    209
  • 8.9 8/16-bit Capture Timer/Counter Operation in Each Mode

    213
  • 8.10 Notes on Using 8/16-bit Capture Timer/Counter

    214
  • 8.11 Program Example for 8/16-bit Capture Timer/Counter

    216
• CHAPTER 9 12-BIT PPG TIMER

  221
  • 9.1 Overview of 12-bit PPG Timer

    222
  • 9.2 Configuration of 12-bit PPG Timer Circuit

    225
  • 9.3 Pin of 12-bit PPG Timer

    227
  • 9.4 Registers of 12-bit PPG Timer

    229
    • 9.4.1 12-bit PPG Control Register 1 (RCR21)

      230
    • 9.4.2 12-bit PPG Control Register 2 (RCR22)

      231
    • 9.4.3 12-bit PPG Control Register 3 (RCR23)

      232
    • 9.4.4 12-bit PPG Control Register 4 (RCR24)

      234
  • 9.5 Operations of 12-bit PPG Timer Functions

    235
  • 9.6 Notes on Using 12-bit PPG Timer

    237
  • 9.7 Program Example for 12-bit PPG Timer

    239
• CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)

  241
  • 10.1 Overview of External Interrupt Circuit 1

    242
  • 10.2 Configuration of External Interrupt Circuit 1

    243
  • 10.3 Pins of External Interrupt Circuit 1

    245
  • 10.4 Registers of External Interrupt Circuit 1

    247
    • 10.4.1 External Interrupt Control Register 1 (EIC1)

      248
    • 10.4.2 External Interrupt Control Register 2 (EIC2)

      251
  • 10.5 Interrupt of External Interrupt Circuit 1

    253
  • 10.6 Operations of External Interrupt Circuit 1

    255
  • 10.7 Program Example for External Interrupt Circuit 1

    257
• CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)

  259
  • 11.1 Overview of External Interrupt Circuit 2

    260
  • 11.2 Configuration of External Interrupt Circuit 2

    261
  • 11.3 Pins of External Interrupt Circuit 2

    262
  • 11.4 Registers of External Interrupt Circuit 2

    265
    • 11.4.1 External Interrupt 2 Control Register (EIE2)

      266
    • 11.4.2 External Interrupt 2 Flag Register (EIF2)

      268
  • 11.5 Interrupt of External Interrupt Circuit 2

    269
  • 11.6 Operations of External Interrupt Circuit 2

    270
  • 11.7 Program Example for External Interrupt Circuit 2

    272
• CHAPTER 12 A/D CONVERTER

  275
  • 12.1 Overview of A/D Converter

    276
  • 12.2 Configuration of A/D Converter

    277
  • 12.3 Pins of A/D Converter

    279
  • 12.4 Registers of A/D Converter

    281
    • 12.4.1 A/D Control Register 1 (ADC1)

      282
    • 12.4.2 A/D Control Register 2 (ADC2)

      284
    • 12.4.3 A/D Data Register (ADDH and ADDL)

      286
    • 12.4.4 A/D Enable Register (ADEN)

      287
  • 12.5 Interrupt of A/D Converter

    288
  • 12.6 Operations of A/D Converter Functions

    289
  • 12.7 Notes on Using A/D Converter

    291
  • 12.8 Program Example for A/D Converter

    293
• CHAPTER 13 UART

  295
  • 13.1 Overview of UART

    296
  • 13.2 Configuration of UART

    300
  • 13.3 Pins of UART

    303
  • 13.4 Registers of UART

    305
    • 13.4.1 Serial Mode Control Register (SMC)

      306
    • 13.4.2 Serial Rate Control Register (SRC)

      308
    • 13.4.3 Serial Status and Data Register (SSD)

      310
    • 13.4.4 Serial Input Data Register (SIDR)

      313
    • 13.4.5 Serial Output Data Register (SODR)

      314
    • 13.4.6 Clock Divider Selection Register (UPC)

      315
    • 13.4.7 Serial Switch Register (SSEL)

      317
  • 13.5 Interrupt of UART

    319
  • 13.6 Operations of UART Functions

    320
    • 13.6.1 Transmission Operations (Operating Mode 0, 1, 2, and 3)

      322
    • 13.6.2 Reception Operations (Operating Mode 0, 1, or 3)

      323
    • 13.6.3 Reception Operations (Operating Mode 2 Only)

      325
  • 13.7 Program Example for UART

    327
• CHAPTER 14 8-BIT SERIAL I/O

  329
  • 14.1 Overview of 8-Bit Serial I/O

    330
  • 14.2 Configuration of 8-Bit Serial I/O

    331
  • 14.3 Pins of 8-Bit Serial I/O

    333
  • 14.4 Registers of 8-Bit Serial I/O

    335
    • 14.4.1 Serial Mode Register (SMR)

      336
    • 14.4.2 Serial Data Register (SDR)

      339
  • 14.5 Interrupt of 8-Bit Serial I/O

    340
  • 14.6 Operations of Serial Output Functions

    341
  • 14.7 Operations of Serial Input Functions

    343
  • 14.8 8-Bit Serial I/O Operation in Each Mode

    345
  • 14.9 Notes on Using 8-Bit Serial I/O

    349
  • 14.10 Example of 8-Bit Serial I/O Connection

    350
  • 14.11 Program Example for 8-Bit Serial I/O

    352
• CHAPTER 15 BUZZER OUTPUT

  355
  • 15.1 Overview of the Buzzer Output

    356
  • 15.2 Configuration of the Buzzer Output

    357
  • 15.3 Pin of the Buzzer Output

    358
  • 15.4 Buzzer Register (BZCR)

    359
  • 15.5 Program Example for Buzzer Output

    361
• CHAPTER 16 WILD REGISTER FUNCTION

  363
  • 16.1 Overview of the Wild Register Function

    364
  • 16.2 Configuration of the Wild Register Function

    365
  • 16.3 Registers of the Wild Register Function

    366
    • 16.3.1 Data Setting Registers (WRDR0 and WRDR1)

      367
    • 16.3.2 Higher Address Set Registers (WRARH0 and WRARH1)

      368
    • 16.3.3 Lower Address Set Registers (WRARL0 and WRARL1)

      369
    • 16.3.4 Address Comparison EN Register (WREN)

      370
    • 16.3.5 Data Test Set Register (WROR)

      371
  • 16.4 Operations of the Wild Register Functions

    372
• CHAPTER 17 FLASH MEMORY

  373
  • 17.1 Overview of Flash Memory

    374
  • 17.2 Flash Memory Control Status Register (FMCS)

    375
  • 17.3 Starting the Flash Memory Automatic Algorithm

    377
  • 17.4 Confirming the Automatic Algorithm Execution State

    378
    • 17.4.1 Data Polling Flag (DQ7)

      379
    • 17.4.2 Toggle Bit Flag (DQ6)

      380
    • 17.4.3 Timing Limit Exceeded Flag (DQ5)

      381
    • 17.4.4 Toggle Bit-2 Flag (DQ2)

      382
  • 17.5 Detailed Explanation of Writing to Erasing Flash Memory

    383
    • 17.5.1 Setting The Read/Reset State

      384
    • 17.5.2 Writing Data

      385
    • 17.5.3 Erasing All Data (Erasing Chips)

      387
  • 17.6 Flash Security Feature

    388
  • 17.7 Notes on using Flash Memory

    389
• APPENDIX

  391
  • APPENDIX A I/O Map

    392
  • APPENDIX B Overview of the Instructions

    396
    • B.1 Addressing

      399
    • B.2 Special Instructions

      403
    • B.3 Bit Manipulation Instructions (SETB and CLRB)

      407
    • B.4 F2MC-8L Instructions List

      408
    • B.5 Instruction Map

      415
  • APPENDIX C Mask Options

    416
  • APPENDIX D Programming EPROM with Evaluation Chip

    417
  • APPENDIX E Pin State of the MB89202/F202RA Series

    418