Manuais de utilizador para Hitachi HTS543280L9SA00

índice analítico

• GENERAL

  9
• 1 INTRODUCTION

  9
• 1.1 Abbreviations

  9
• 1.2 References

  12
• 1.3 General caution

  12
• 1.4 Drive handling precautions

  12
• 2 OUTLINE OF THE DRIVE

  13
• PART 1 FUNCTIONAL SPECIFICATION

  14
• 3 FIXED DISK SUBSYSTEM DESCRIPTION

  15
• Control Electronics

  15
• Head disk assembly data

  15
• 4 FIXED DISK CHARACTERISTICS

  16
• Formatted capacity by model number

  16
• Data sheet

  17
• Cylinder allocation

  17
• Performance characteristics

  18
• 5 DATA INTEGRITY

  22
• Data loss on power off

  22
• Write Cache

  22
• Equipment status

  22
• WRITE safety

  22
• Data buffer test

  23
• Error recovery

  23
• Automatic reallocation

  23
• ECC

  24
• 6 SPECIFICATION

  25
• Environment

  25
• DC power requirements

  27
• Reliability

  29
• Mechanical specifications

  32
• Vibration and shock

  34
• Acoustics

  36
• Identification labels

  37
• Electromagnetic compatibility

  37
• Safety

  38
• 6.10 Packaging

  38
• 6.11 Substance restriction requirements

  38
• 7 ELECTRICAL INTERFACE SPECIFICATIONS

  39
• Cabling

  39
• Interface connector

  39
• Signal definitions

  40
• PART 2 INTERFACE SPECIFICATION

  44
• 8 GENERAL

  45
• Introduction

  45
• Terminology

  45
• 9 DEVIATIONS FROM STANDARD

  46
• 10 PHYSICAL INTERFACE

  46
• 11 REGISTERS

  46
• 11.1 Register naming convention

  47
• 11.2 Command register

  47
• 11.3 Device Control Register

  47
• 11.4 Device Register

  48
• 11.5 Error Register

  48
• 11.6 Features Register

  48
• 11.7 LBA High Register

  49
• 11.8 LBA Low Register

  49
• 11.9 LBA Mid Register

  49
• 11.10 Sector Count Register

  49
• 11.11 Status Register

  49
• 12 GENERAL OPERATION DESCRIPTIONS

  51
• 12.1 Reset Response

  51
• 12.2 Diagnostic and Reset considerations

  52
• 12.3 Power-off considerations

  53
• 12.4 Sector Addressing Mode

  54
• 12.5 Power Management Feature

  54
• 12.6 Advanced Power Management (Adaptive Battery Life Extender 3) Feature

  56
• 12.7 Interface Power Management Mode (Slumber and Partial)

  57
• 12.8 S.M.A.R.T. Function

  57
• 12.9 Security Mode Feature Set

  58
• 12.10 Protected Area Function

  64
• 12.11 Seek Overlap

  67
• 12.12 Write Cache Function

  67
• 12.13 Reassign Function

  67
• 12.14 48-bit Address Feature Set

  68
• 12.15 Software Setting Preservation Feature Set

  69
• 12.16 Native Command Queuing

  70
• 12.17 SMART Command Transport (SCT)

  70
• 13 COMMAND PROTOCOL

  72
• 13.1 Data In Commands

  72
• 13.2 Data Out Commands

  72
• 13.3 Non-Data Commands

  73
• 13.4 DMA Data Transfer Commands

  74
• 13.5 First-parity DMA Commands

  74
• 14 COMMAND DESCRIPTIONS

  75
• 14.1 Check Power Mode (E5h/98h)

  79
• 14.2 Device Configuration Overlay (B1h)

  80
• 14.3 Download Microcode (92h)

  84
• 14.4 Execute Device Diagnostic (90h)

  86
• 14.5 Flush Cache (E7h)

  87
• 14.6 Flush Cache Ext (EAh)

  88
• 14.7 Format Track (50h: Vendor Specific)

  89
• 14.8 Format Unit (F7h: Vendor Specific)

  90
• 14.9 Identify Device (ECh)

  91
• 14.10 Idle (E3h/97h)

  103
• 14.11 Idle Immediate (E1h/95h)

  104
• 14.12 Initialize Device Parameters (91h)

  105
• 14.13 Read Buffer (E4h)

  106
• 14.14 Read DMA(C8h/C9h)

  107
• 14.15 Read DMA Ext (25h)

  108
• 14.16 Read FPDMA Queued (60h)

  109
• 14.17 Read Log Ext(2Fh)

  110
• 14.18 Read Multiple (C4h)

  118
• 14.19 Read Multiple Ext (29h)

  119
• 14.20 Read Native Max Address (F8h)

  120
• 14.21 Read Native Max Address Ext (27h)

  121
• 14.22 Read Sector(s) (20h/21h)

  122
• 14.23 Read Sector(s) Ext (24h)

  123
• 14.24 Read Verify Sector(s) (40h/41h)

  124
• 14.25 Read Verify Sector(s) Ext (42h)

  125
• 14.26 Recalibrate (1xh)

  126
• 14.27 Security Disable Password (F6h)

  127
• 14.28 Security Erase Prepare (F3h)

  128
• 14.29 Security Erase Unit (F4h)

  129
• 14.30 Security Freeze Lock (F5h)

  131
• 14.31 Security Set Password (F1h)

  132
• 14.32 Security Unlock (F2h)

  134
• 14.33 Seek (7xh)

  135
• 14.34 Sense Condition (F0h : vendor specific)

  136
• 14.35 Set Features (EFh)

  137
• 14.36 Set Max Address (F9h)

  139
• 14.37 Set Max Address Ext (37h)

  141
• 14.38 Set Multiple (C6h)

  143
• 14.39 Sleep (E6h/99h)

  144
• 14.40 S.M.A.R.T Function Set (B0h)

  145
• 14.41 Standby (E2h/96h)

  160
• 14.42 Standby Immediate (E0h/94h)

  161
• 14.43 Write Buffer (E8h)

  162
• 14.44 Write DMA (CAh/CBh)

  163
• 14.45 Write DMA Ext (35h)

  164
• 14.46 Write DMA FUA Ext (3Dh)

  165
• 14.47 Write FPDMA Queued (61h)

  166
• 14.48 Write Log Ext (3Fh)

  167
• 14.49 Write Multiple (C5h)

  168
• 14.50 Write Multiple Ext (39h)

  169
• 14.51 Write Multiple FUA Ext (CEh)

  170
• 14.52 Write Sector(s) (30h/31h)

  171
• 14.53 Write Sector(s) Ext (34h)

  172
• 14.54 Write Uncorrectable Ext (45h)

  173
• 15 TIMINGS

  175