Manuais de utilizador para Intel i3-3229Y

índice analítico

• Desktop 3rd Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

  1
• Revision History

  8
• 1 Introduction

  9
  • 1.1 Processor Feature Details

    11
    • 1.1.1 Supported Technologies

      11
  • 1.2 Interfaces

    11
    • 1.2.1 System Memory Support

      11
    • 1.2.2 PCI Express*

      12
    • 1.2.3 Direct Media Interface (DMI)

      14
    • 1.2.4 Platform Environment Control Interface (PECI)

      14
    • 1.2.5 Processor Graphics

      14
    • 1.2.6 Intel® Flexible Display Interface (Intel® FDI)

      15
  • 1.3 Power Management Support

    15
    • 1.3.1 Processor Core

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    • 1.3.2 System

      15
    • 1.3.3 Memory Controller

      15
    • 1.3.4 PCI Express*

      15
    • 1.3.5 Direct Media Interface (DMI)

      16
    • 1.3.6 Processor Graphics Controller (GT)

      16
    • 1.3.7 Thermal Management Support

      16
  • 1.4 Processor SKU Definitions

    16
  • 1.5 Package

    17
  • 1.6 Processor Compatibility

    18
  • 1.7 Terminology

    19
  • 1.8 Related Documents

    22
• 2 Interfaces

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  • 2.1 System Memory Interface

    23
    • 2.1.1 System Memory Technology Supported

      23
    • 2.1.2 System Memory Timing Support

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    • 2.1.3 System Memory Organization Modes

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      • 2.1.3.1 Single-Channel Mode

        25
      • 2.1.3.2 Dual-Channel Mode – Intel® Flex Memory Technology Mode

        25
    • 2.1.4 Rules for Populating Memory Slots

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    • 2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)

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      • 2.1.5.1 Just-in-Time Command Scheduling

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      • 2.1.5.2 Command Overlap

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      • 2.1.5.3 Out-of-Order Scheduling

        27
    • 2.1.6 Data Scrambling

      27
    • 2.1.7 DDR3 Reference Voltage Generation

      27
  • 2.2 PCI Express* Interface

    28
    • 2.2.1 PCI Express* Architecture

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      • 2.2.1.1 Transaction Layer

        29
      • 2.2.1.2 Data Link Layer

        29
      • 2.2.1.3 Physical Layer

        29
    • 2.2.2 PCI Express* Configuration Mechanism

      30
    • 2.2.3 PCI Express* Port

      31
      • 2.2.3.1 PCI Express* Lanes Connection

        31
  • 2.3 Direct Media Interface (DMI)

    32
    • 2.3.1 DMI Error Flow

      32
    • 2.3.2 Processor / PCH Compatibility Assumptions

      32
    • 2.3.3 DMI Link Down

      32
  • 2.4 Processor Graphics Controller (GT)

    33
    • 2.4.1 3D and Video Engines for Graphics Processing

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      • 2.4.1.1 3D Engine Execution Units

        33
      • 2.4.1.2 3D Pipeline

        34
      • 2.4.1.3 Video Engine

        34
      • 2.4.1.4 2D Engine

        35
    • 2.4.2 Processor Graphics Display

      36
      • 2.4.2.1 Display Planes

        36
      • 2.4.2.2 Display Pipes

        37
      • 2.4.2.3 Display Ports

        37
    • 2.4.3 Intel® Flexible Display Interface (Intel® FDI)

      37
    • 2.4.4 Multi Graphics Controllers Multi-Monitor Support

      37
  • 2.5 Platform Environment Control Interface (PECI)

    38
  • 2.6 Interface Clocking

    38
    • 2.6.1 Internal Clocking Requirements

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• 3 Technologies

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  • 3.1 Intel® Virtualization Technology (Intel® VT)

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    • 3.1.1 Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) Objectives

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    • 3.1.2 Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) Features

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    • 3.1.3 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Objectives

      40
    • 3.1.4 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Features

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    • 3.1.5 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Features Not Supported

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  • 3.2 Intel® Trusted Execution Technology (Intel® TXT)

    42
  • 3.3 Intel® Hyper-Threading Technology (Intel® HT Technology)

    42
  • 3.4 Intel® Turbo Boost Technology

    43
    • 3.4.1 Intel® Turbo Boost Technology Frequency

      43
    • 3.4.2 Intel® Turbo Boost Technology Graphics Frequency

      43
  • 3.5 Intel® Advanced Vector Extensions (Intel® AVX)

    44
  • 3.6 Security and Cryptography Technologies

    44
    • 3.6.1 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)

      44
    • 3.6.2 PCLMULQDQ Instruction

      44
    • 3.6.3 RDRAND Instruction

      45
  • 3.7 Intel® 64 Architecture x2APIC

    45
  • 3.8 Supervisor Mode Execution Protection (SMEP)

    46
  • 3.9 Power Aware Interrupt Routing (PAIR)

    46
• 4 Power Management

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  • 4.1 Advanced Configuration and Power Interface (ACPI) States Supported

    48
    • 4.1.1 System States

      48
    • 4.1.2 Processor Core / Package Idle States

      48
    • 4.1.3 Integrated Memory Controller States

      48
    • 4.1.4 PCI Express* Link States

      49
    • 4.1.5 Direct Media Interface (DMI) States

      49
    • 4.1.6 Processor Graphics Controller States

      49
    • 4.1.7 Interface State Combinations

      49
  • 4.2 Processor Core Power Management

    50
    • 4.2.1 Enhanced Intel® SpeedStep® Technology

      50
    • 4.2.2 Low-Power Idle States

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    • 4.2.3 Requesting Low-Power Idle States

      52
    • 4.2.4 Core C-states

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      • 4.2.4.1 Core C0 State

        52
      • 4.2.4.2 Core C1 / C1E State

        53
      • 4.2.4.3 Core C3 State

        53
      • 4.2.4.4 Core C6 State

        53
      • 4.2.4.5 C-State Auto-Demotion

        53
    • 4.2.5 Package C-States

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      • 4.2.5.1 Package C0

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      • 4.2.5.2 Package C1/C1E

        55
      • 4.2.5.3 Package C3 State

        56
      • 4.2.5.4 Package C6 State

        56
  • 4.3 Integrated Memory Controller (IMC) Power Management

    56
    • 4.3.1 Disabling Unused System Memory Outputs

      56
    • 4.3.2 DRAM Power Management and Initialization

      57
      • 4.3.2.1 Initialization Role of CKE

        58
      • 4.3.2.2 Conditional Self-Refresh

        58
      • 4.3.2.3 Dynamic Power Down Operation

        59
      • 4.3.2.4 DRAM I/O Power Management

        59
    • 4.3.3 DDR Electrical Power Gating (EPG)

      59
  • 4.4 PCI Express* Power Management

    60
  • 4.5 DMI Power Management

    60
  • 4.6 Graphics Power Management

    60
    • 4.6.1 Intel® Rapid Memory Power Management (Intel® RMPM) (also known as CxSR)

      60
    • 4.6.2 Intel® Graphics Performance Modulation Technology (Intel® GPMT)

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    • 4.6.3 Graphics Render C-State

      60
    • 4.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT)

      61
    • 4.6.5 Intel® Graphics Dynamic Frequency

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  • 4.7 Graphics Thermal Power Management

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• 5 Thermal Management

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• 6 Signal Description

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  • 6.1 System Memory Interface Signals

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  • 6.2 Memory Reference and Compensation Signals

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  • 6.3 Reset and Miscellaneous Signals

    68
  • 6.4 PCI Express*-based Interface Signals

    69
  • 6.5 Intel® Flexible Display (Intel® FDI) Interface Signals

    69
  • 6.6 Direct Media Interface (DMI) Signals

    70
  • 6.7 Phase Lock Loop (PLL) Signals

    70
  • 6.8 Test Access Points (TAP) Signals

    70
  • 6.9 Error and Thermal Protection Signals

    71
  • 6.10 Power Sequencing Signals

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  • 6.11 Processor Power Signals

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  • 6.12 Sense Signals

    73
  • 6.13 Ground and Non-Critical to Function (NCTF) Signals

    74
  • 6.14 Processor Internal Pull-Up / Pull-Down Resistors

    74
• 7 Electrical Specifications

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  • 7.1 Power and Ground Lands

    75
  • 7.2 Decoupling Guidelines

    75
    • 7.2.1 Voltage Rail Decoupling

      75
  • 7.3 Processor Clocking (BCLK[0], BCLK#[0])

    76
    • 7.3.1 Phase Lock Loop (PLL) Power Supply

      76
  • 7.4 VCC Voltage Identification (VID)

    76
  • 7.5 System Agent (SA) VCC VID

    80
  • 7.6 Reserved or Unused Signals

    80
  • 7.7 Signal Groups

    80
  • 7.8 Test Access Port (TAP) Connection

    82
  • 7.9 Storage Conditions Specifications

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  • 7.10 DC Specifications

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    • 7.10.1 Voltage and Current Specifications

      84
  • 7.11 Platform Environmental Control Interface (PECI) DC Specifications

    90
    • 7.11.1 PECI Bus Architecture

      90
    • 7.11.2 DC Characteristics

      91
    • 7.11.3 Input Device Hysteresis

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• 8 Processor Land and Signal Information

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  • 8.1 Processor Land Assignments

    93
• 9 DDR Data Swizzling

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