Manual Do Utilizador (80525KY5501M)índice analíticoIntroduction9Terminology9Introduction9Terminology91.1.1 S.E.C. Cartridge Terminology10References101.1.1 S.E.C. Cartridge Terminology10References10Electrical Specifications11The Pentium® III Xeon™ Processor System Bus and VREF11Electrical Specifications11The Pentium® III Xeon™ Processor System Bus and VREF11Power and Ground Pins12Decoupling Guidelines12Power and Ground Pins12Decoupling Guidelines122.3.1 Pentium® III Xeon™ Processor VCCCORE132.3.2 Level 2 Cache Decoupling132.3.3 System Bus AGTL+ Decoupling13System Bus Clock and Processor Clocking132.3.1 Pentium® III Xeon™ Processor VCCCOR132.3.2 Level 2 Cache Decoupling132.3.3 System Bus AGTL+ Decoupling13System Bus Clock and Processor Clocking13Core Frequency to System Bus Multiplier Configuration14Core Frequency to System Bus Multiplier Configuration142.4.1 Mixing Processors15Timing Diagram of Clock Ratio Signals15Logical Schematic for Clock Ratio Pin Sharing152.4.1 Mixing Processors15Timing Diagram of Clock Ratio Signals15Logical Schematic for Clock Ratio Pin Sharing15Voltage Identification16Core and L2 Voltage Identification Definition16Voltage Identification16Core and L2 Voltage Identification Definition 1, 216System Bus Unused Pins and Test Pins17System Bus Unused Pins and Test Pins17System Bus Signal Groups18Pentium® III Xeon™ Processor System Bus Pin Groups18System Bus Signal Groups18Pentium® III Xeon™ Processor System Bus Pin Groups182.7.1 Asynchronous vs. Synchronous for System Bus Signals19Test Access Port (TAP) Connection192.7.1 Asynchronous vs. Synchronous for System Bus Signals19Test Access Port (TAP) Connection19Maximum Ratings20Processor DC Specifications20Pentium® III Xeon™ Processor Absolute Maximum Ratings20Maximum Ratings20Processor DC Specifications20Pentium® III Xeon™ Processor Absolute Maximum Ratings20Voltage Specifications21Voltage Specifications 121Current Specifications22Current Specifications 122I-V Curve for nMOS Device23AGTL+ Signal Groups, DC Specifications at the Processor Core23I-V Curve for nMOS Device23AGTL+ Signal Groups, DC Specifications at the Processor Core23AGTL+ System Bus Specifications24Processor Core24SMBus Signal Group, DC Specifications at the Processor Core24AGTL+ System Bus Specifications24SMBus Signal Group, DC Specifications at the Processor Core24System Bus AC Specifications25Pentium® III Xeon™ Processor Internal Parameters for the AGTL+ Bus25System Bus AC Specifications (Clock) at the Processor Core25System Bus AC Specifications25Pentium® III Xeon™ Processor Internal Parameters for the AGTL+ Bus25System Bus AC Specifications (Clock) at the Processor Core25Processor Core26System Bus AC Specifications (Reset Conditions)27Core27System Bus AC Specifications (Reset Conditions)27System Bus AC Specifications (TAP Connection) at the Processor Core28SMBus Signal Group, AC Specifications at the Edge Fingers28System Bus AC Specifications (TAP Connection) at the Processor Core 128SMBus Signal Group, AC Specifications at the Edge Fingers28BCLK, PICCLK, TCK Generic Clock Waveform29SMBCLK Clock Waveform29Valid Delay Timings29BCLK, PICCLK, TCK Generic Clock Waveform29SMBCLK Clock Waveform29Valid Delay Timings29Setup and Hold Timings30FRC Mode BCLK to PICCLK Timing30Setup and Hold Timings30FRC Mode BCLK to PICCLK Timing30System Bus Reset and Configuration Timings31Power-On Reset and Configuration Timings31System Bus Reset and Configuration Timings31Power-On Reset and Configuration Timings31Signal Quality32Test Timings (Boundary Scan)32Test Reset Timings32Signal Quality32Test Timings (Boundary Scan)32Test Reset Timings32System Bus Clock Signal Quality Specifications33AGTL+ Signal Quality Specifications33BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins33BCLK Signal Quality Specifications for Simulation at the Processor Core33System Bus Clock Signal Quality Specifications33AGTL+ Signal Quality Specifications33BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins33BCLK Signal Quality Specifications for Simulation at the Processor Core 1333.2.1 AGTL+ Ringback Tolerance Specifications343.2.2 AGTL+ Overshoot/Undershoot Guidelines34Low to High AGTL+ Receiver Ringback Tolerance34Core343.2.1 AGTL+ Ringback Tolerance Specifications343.2.2 AGTL+ Overshoot/Undershoot Guidelines34Low to High AGTL+ Receiver Ringback Tolerance34Non-AGTL+ Signal Quality Specifications353.3.1 2.5 V Tolerant Buffer Overshoot/Undershoot Guidelines353.3.2 2.5 V Tolerant Buffer Ringback Specification35Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback35AGTL+ Overshoot/Undershoot Guidelines at the Processor Core35Non-AGTL+ Signal Quality Specifications353.3.1 2.5 V Tolerant Buffer Overshoot/Undershoot Guidelines353.3.2 2.5 V Tolerant Buffer Ringback Specification35Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback35AGTL+ Overshoot/Undershoot Guidelines at the Processor Core353.3.3 2.5 V Tolerant Buffer Settling Limit Guideline36Processor Features36Functional Redundancy Checking Mode36Processor Core363.3.3 2.5 V Tolerant Buffer Settling Limit Guideline36Processor Features36Functional Redundancy Checking Mode36Low Power States and Clock Control374.2.1 Normal State— State 1374.2.2 Auto Halt Power Down State — State 237Low Power States and Clock Control374.2.1 Normal State— State 1374.2.2 Auto Halt Power Down State — State 2374.2.3 Stop-Grant State — State 338Stop Clock State Machine384.2.3 Stop-Grant State — State 338Stop Clock State Machine384.2.4 Halt/Grant Snoop State — State 4394.2.5 Sleep State — State 5394.2.6 Clock Control394.2.4 Halt/Grant Snoop State — State 4394.2.5 Sleep State — State 5394.2.6 Clock Control39System Management Bus (SMBus) Interface40Logical Schematic of SMBus Circuitry40System Management Bus (SMBus) Interface40Logical Schematic of SMBus Circuitry404.3.1 Processor Information ROM41Processor Information ROM Format414.3.1 Processor Information ROM41Processor Information ROM Format414.3.2 Scratch EEPROM424.3.2 Scratch EEPROM42SMBus Transactions43Thermal Sensor43Current Address Read SMBus Packet43Random Address Read SMBus Packet43Byte Write SMBus Packet434.3.4 Thermal Sensor43Current Address Read SMBus Packet43Random Address Read SMBus Packet43Byte Write SMBus Packet43Thermal Sensor Supported SMBus Transactions444.3.5 Thermal Sensor Supported SMBus Transactions44Write Byte SMBus Packet45Read Byte SMBus Packet45Send Byte SMBus Packet45Receive Byte SMBus Packet45ARA SMBus Packet45Command Byte Bit Assignments45Write Byte SMBus Packet45Read Byte SMBus Packet45Send Byte SMBus Packet45Receive Byte SMBus Packet45ARA SMBus Packet45Command Byte Bit Assignments45Thermal Sensor Registers464.3.6.1 Thermal Reference Registers464.3.6.2 Thermal Limit Registers464.3.6.3 Status Register464.3.6 Thermal Sensor Registers464.3.6.1 Thermal Reference Registers464.3.6.2 Thermal Limit Registers464.3.6.3 Status Register464.3.6.4 Configuration Register474.3.6.5 Conversion Rate Register47Thermal Sensor Status Register47Thermal Sensor Configuration Register474.3.6.4 Configuration Register474.3.6.5 Conversion Rate Register47Thermal Sensor Status Register47Thermal Sensor Configuration Register47SMBus Device Addressing48Thermal Sensor Conversion Rate Register48SMBus Device Addressing48Thermal Sensor Conversion Rate Register48Thermal Specifications and Design Considerations49Thermal Sensor SMBus Addressing on the Pentium® III Xeon™ Processor49Memory Device SMBus Addressing on the Pentium® III Xeon™ Processor49Thermal Specifications and Design Considerations49Thermal Sensor SMBus Addressing on the Pentium® III Xeon™ Processor49Memory Device SMBus Addressing on the Pentium® III Xeon™ Processor49Thermal Specifications505.1.1 Power Dissipation50Thermal Plate View50Thermal Specifications505.1.1 Power Dissipation50Thermal Plate View505.1.2 Plate Flatness Specification51Processor Thermal Analysis515.2.1 Thermal Solution Performance51Plate Flatness Reference51Thermal Design Power515.1.2 Plate Flatness Specification51Processor Thermal Analysis515.2.1 Thermal Solution Performance51Plate Flatness Reference51Thermal Design Power 1515.2.2 Thermal Plate to Heat Sink Interface Management Guide525.2.2 Thermal Plate to Heat Sink Interface Management Guide525.2.3 Measurements for Thermal Specifications535.2.3.1 Thermal Plate Temperature Measurement53Measurement Points535.2.3 Measurements for Thermal Specifications535.2.3.1 Thermal Plate Temperature Measurement535.2.3.2 Cover Temperature Measurement Guideline54Technique for Measuring TPLATE with 0° Angle Attachment54Technique for Measuring TPLATE with 90° Angle Attachment545.2.3.2 Cover Temperature Measurement Guideline54Technique for Measuring TPLATE with 0° Angle Attachment54Technique for Measuring TPLATE with 90° Angle Attachment54Mechanical Specifications55Placement55Mechanical Specifications55Isometric View of Pentium® III Xeon™ Processor S.E.C. Cartridge56Isometric View of Pentium® III Xeon™ Processor S.E.C. Cartridge56S.E.C. Cartridge Cooling Solution Attach Details (Notes follow Figure 27)57S.E.C. Cartridge Cooling Solution Attach Details (Notes follow Figure 27)57S.E.C. Cartridge Retention Enabling Details (Notes follow Figure 27)58S.E.C. Cartridge Retention Enabling Details (Notes follow Figure 27)58S.E.C. Cartridge Retention Enabling Details59S.E.C. Cartridge Retention Enabling Details59Weight60Cartridge to Connector Mating Details60Side View of Connector Mating Details60Weight60Cartridge to Connector Mating Details60Side View of Connector Mating Details60Top View of Cartridge Insertion Pressure Points61Front View of Connector Mating Details61Top View of Cartridge Insertion Pressure Points61Front View of Connector Mating Details61Pentium® III Xeon™ Processor Substrate Edge Finger Signal Listing62Signal Listing in Order by Pin Number62Pentium® III Xeon™ Processor Substrate Edge Finger Signal Listing62Signal Listing in Order by Pin Number62Signal Listing in Order by Pin Name66Signal Listing in Order by Pin Name66Boxed Processor Specifications71Introduction71Mechanical Specifications71Boxed Pentium® III Xeon™ Processor71Boxed Processor Specifications71Introduction71Mechanical Specifications71Boxed Pentium® III Xeon™ Processor71Side View Space Requirements for the Boxed Processor72Side View Space Requirements for the Boxed Processor727.2.1 Boxed Processor Heatsink Dimensions737.2.2 Boxed Processor Heatsink Weight737.2.3 Boxed Processor Retention Mechanism73Front View Space Requirements for the Boxed Processor73Boxed Processor Heatsink Dimensions737.2.1 Boxed Processor Heatsink Dimensions737.2.2 Boxed Processor Heatsink Weight737.2.3 Boxed Processor Retention Mechanism73Front View Space Requirements for the Boxed Processor73Boxed Processor Heatsink Dimensions73Thermal Specifications747.3.1 Boxed Processor Cooling Requirements747.3.2 Optional Auxiliary Fan Attachment74Thermal Specifications747.3.1 Boxed Processor Cooling Requirements747.3.2 Optional Auxiliary Fan Attachment74(Not Included with Boxed Processor)75(Fan Not Included)757.3.2.1 Clearance Recommendations for Auxiliary Fan76(Grommet Shown)76Side View Space Recommendation for the Auxiliary Fan767.3.2.1 Clearance Recommendations for Auxiliary Fan76Side View Space Recommendation for the Auxiliary Fan767.3.2.2 Fan Power Recommendations for Auxiliary Fan77Front View Space Recommendations for the Auxiliary Fan77Boxed Processor Fan/Heatsink Power Cable Connector Description777.3.2.2 Fan Power Recommendations for Auxiliary Fan77Front View Space Recommendations for the Auxiliary Fan77Boxed Processor Fan/Heatsink Power Cable Connector Description777.3.2.3 Thermal Evaluation for Auxiliary Fan78Integration Tools78In-Target Probe (ITP) for Pentium® III Xeon™ Processors78Fan/Heatsink Power and Signal Specifications787.3.2.3 Thermal Evaluation for Auxiliary Fan78Integration Tools78In-Target Probe (ITP) for Pentium® III Xeon™ Processors78Fan/Heatsink Power and Signal Specifications788.1.1 Primary Function798.1.2 Debug Port Connector Description79Hardware Components of an ITP798.1.1 Primary Function798.1.2 Debug Port Connector Description79Hardware Components of an ITP798.1.3 Debug Port Signal Descriptions80Debug Port Pinout Description and Requirements808.1.3 Debug Port Signal Descriptions80Debug Port Pinout Description and Requirements 1808.1.4 Debug Port Signal Notes82AGTL+ Signal Termination828.1.4 Debug Port Signal Notes82AGTL+ Signal Termination828.1.4.1 General Signal Quality Notes838.1.4.2 Signal Note: DBRESET#838.1.4.3 Signal Note: TDO and TDI838.1.4.4 Signal Note: TCK838.1.4.1 General Signal Quality Notes838.1.4.2 Signal Note: DBRESET#838.1.4.3 Signal Note: TDO and TDI838.1.4.4 Signal Note: TCK83TCK with Individual Buffering Scheme84TCK with Individual Buffering Scheme848.1.5 Using Boundary Scan to Communicate to the Processor85System Preferred Debug Port Layout858.1.5 Using Boundary Scan to Communicate to the Processor85System Preferred Debug Port Layout85Integration Tool (Logic Analyzer) Considerations86Appendix86Alphabetical Signals Reference869.1.1 A[35:03]# (I/O)869.1.2 A20M# (I)86Integration Tool (Logic Analyzer) Considerations86Appendix86Alphabetical Signals Reference869.1.1 A[35:03]# (I/O)86A20M# (I)869.1.3 ADS# (I/O)879.1.4 AERR# (I/O)879.1.5 AP[1:0]# (I/O)879.1.6 BCLK (I)879.1.7 BERR# (I/O)87ADS# (I/O)87AERR# (I/O)87AP[1:0]# (I/O)87BCLK (I)87BERR# (I/O)879.1.8 BINIT# (I/O)889.1.9 BNR# (I/O)889.1.10 BP[3:2]# (I/O)889.1.11 BPM[1:0]# (I/O)889.1.12 BPRI# (I)889.1.13 BR0# (I/O), BR[3:1]# (I)88BINIT# (I/O)88BNR# (I/O)88BP[3:2]# (I/O)88BPM[1:0]# (I/O)88BPRI# (I)88BR0# (I/O), BR[3:1]# (I)889.1.14 CPU_SENSE899.1.15 D[63:00]# (I/O)89BR[3:0]# Signals Rotating Interconnect, 4-Way System89BR[3:0]# Signals Rotating Interconnect, 2-Way System89Agent ID Configuration89CPU_SENSE89D[63:00]# (I/O)89BR[3:0]# Signals Rotating Interconnect, 4-Way System89BR[3:0]# Signals Rotating Interconnect, 2-Way System89Agent ID Configuration899.1.16 DBSY# (I/O)909.1.17 DEFER# (I)909.1.18 DEP[7:0]# (I/O)909.1.19 DRDY# (I/O)909.1.20 EMI909.1.21 FERR# (O)909.1.22 FLUSH# (I)90DBSY# (I/O)90DEFER# (I)90DEP[7:0]# (I/O)90DRDY# (I/O)90EMI90FERR# (O)90FLUSH# (I)909.1.23 FRCERR (I/O)919.1.24 HIT# (I/O), HITM# (I/O)919.1.25 IERR# (O)919.1.26 IGNNE# (I)91FRCERR (I/O)91HIT# (I/O), HITM# (I/O)91IERR# (O)91IGNNE# (I)919.1.27 INIT# (I)929.1.28 INTR - see LINT0929.1.29 LINT[1:0] (I)929.1.30 LOCK# (I/O)92INIT# (I)92INTR - see LINT092LINT[1:0] (I)92LOCK# (I/O)929.1.31 L2_SENSE939.1.32 NMI - See LINT1939.1.33 PICCLK (I)939.1.34 PICD[1:0] (I/O)939.1.35 PM[1:0]# (O)939.1.36 PRDY# (O)939.1.37 PREQ# (I)939.1.38 PWREN[1:0] (I)939.1.39 PWRGOOD (I)93L2_SENSE93NMI - See LINT193PICCLK (I)93PICD[1:0] (I/O)93PM[1:0]# (O)93PRDY# (O)93PREQ# (I)93PWREN[1:0] (I)93PWRGOOD (I)939.1.40 REQ[4:0]# (I/O)949.1.41 RESET# (I)94PWRGOOD Relationship at Power-On94REQ[4:0]# (I/O)94RESET# (I)94PWRGOOD Relationship at Power-On949.1.42 RP# (I/O)959.1.43 RS[2:0]# (I)959.1.44 RSP# (I)959.1.45 SA[2:0] (I)95RP# (I/O)95RS[2:0]# (I)95RSP# (I)95SA[2:0] (I)959.1.46 SELFSB[1:0] (I/O)969.1.47 SLP# (I)969.1.48 SMBALERT# (O)969.1.49 SMBCLK (I)969.1.50 SMBDAT (I/O)969.1.51 SMI# (I)96SELFSB[1:0] (I/O)96SLP# (I)96SMBALERT# (O)96SMBCLK (I)96SMBDAT (I/O)96SMI# (I)969.1.52 STPCLK# (I)979.1.53 TCK (I)979.1.54 TDI (I)979.1.55 TDO (O)979.1.56 TEST_25_A62 (I)979.1.57 TEST_VCC_CORE_XXX (I)979.1.58 THERMTRIP# (O)979.1.52 STPCLK# (I)979.1.53 TCK (I)979.1.54 TDI (I)979.1.55 TDO (O)979.1.56 TEST_25_A62 (I)979.1.57 TEST_VCC_CORE_XXX (I)979.1.58 THERMTRIP# (O)979.1.59 TMS (I)989.1.60 TRDY# (I)989.1.61 TRST# (I)989.1.62 VID_L2[4:0], VID_CORE[4:0](O)989.1.63 WP (I)98Signal Summaries98Output Signals989.1.59 TMS (I)989.1.60 TRDY# (I)989.1.61 TRST# (I)989.1.62 VID_L2[4:0], VID_CORE[4:0](O)989.1.63 WP (I)98Signal Summaries98Output Signals †98Input Signals199Input Signals 199I/O Signals (Single Driver)100I/O Signals (Multiple Driver)100I/O Signals (Single Driver)100I/O Signals (Multiple Driver)100Tamanho: 2 MBPáginas: 112Language: EnglishAbrir o manual
Manual Do Utilizador (80525KY550512)índice analíticoIntroduction9Terminology9Introduction9Terminology91.1.1 S.E.C. Cartridge Terminology10References101.1.1 S.E.C. Cartridge Terminology10References10Electrical Specifications11The Pentium® III Xeon™ Processor System Bus and VREF11Electrical Specifications11The Pentium® III Xeon™ Processor System Bus and VREF11Power and Ground Pins12Decoupling Guidelines12Power and Ground Pins12Decoupling Guidelines122.3.1 Pentium® III Xeon™ Processor VCCCORE132.3.2 Level 2 Cache Decoupling132.3.3 System Bus AGTL+ Decoupling13System Bus Clock and Processor Clocking132.3.1 Pentium® III Xeon™ Processor VCCCOR132.3.2 Level 2 Cache Decoupling132.3.3 System Bus AGTL+ Decoupling13System Bus Clock and Processor Clocking13Core Frequency to System Bus Multiplier Configuration14Core Frequency to System Bus Multiplier Configuration142.4.1 Mixing Processors15Timing Diagram of Clock Ratio Signals15Logical Schematic for Clock Ratio Pin Sharing152.4.1 Mixing Processors15Timing Diagram of Clock Ratio Signals15Logical Schematic for Clock Ratio Pin Sharing15Voltage Identification16Core and L2 Voltage Identification Definition16Voltage Identification16Core and L2 Voltage Identification Definition 1, 216System Bus Unused Pins and Test Pins17System Bus Unused Pins and Test Pins17System Bus Signal Groups18Pentium® III Xeon™ Processor System Bus Pin Groups18System Bus Signal Groups18Pentium® III Xeon™ Processor System Bus Pin Groups182.7.1 Asynchronous vs. Synchronous for System Bus Signals19Test Access Port (TAP) Connection192.7.1 Asynchronous vs. Synchronous for System Bus Signals19Test Access Port (TAP) Connection19Maximum Ratings20Processor DC Specifications20Pentium® III Xeon™ Processor Absolute Maximum Ratings20Maximum Ratings20Processor DC Specifications20Pentium® III Xeon™ Processor Absolute Maximum Ratings20Voltage Specifications21Voltage Specifications 121Current Specifications22Current Specifications 122I-V Curve for nMOS Device23AGTL+ Signal Groups, DC Specifications at the Processor Core23I-V Curve for nMOS Device23AGTL+ Signal Groups, DC Specifications at the Processor Core23AGTL+ System Bus Specifications24Processor Core24SMBus Signal Group, DC Specifications at the Processor Core24AGTL+ System Bus Specifications24SMBus Signal Group, DC Specifications at the Processor Core24System Bus AC Specifications25Pentium® III Xeon™ Processor Internal Parameters for the AGTL+ Bus25System Bus AC Specifications (Clock) at the Processor Core25System Bus AC Specifications25Pentium® III Xeon™ Processor Internal Parameters for the AGTL+ Bus25System Bus AC Specifications (Clock) at the Processor Core25Processor Core26System Bus AC Specifications (Reset Conditions)27Core27System Bus AC Specifications (Reset Conditions)27System Bus AC Specifications (TAP Connection) at the Processor Core28SMBus Signal Group, AC Specifications at the Edge Fingers28System Bus AC Specifications (TAP Connection) at the Processor Core 128SMBus Signal Group, AC Specifications at the Edge Fingers28BCLK, PICCLK, TCK Generic Clock Waveform29SMBCLK Clock Waveform29Valid Delay Timings29BCLK, PICCLK, TCK Generic Clock Waveform29SMBCLK Clock Waveform29Valid Delay Timings29Setup and Hold Timings30FRC Mode BCLK to PICCLK Timing30Setup and Hold Timings30FRC Mode BCLK to PICCLK Timing30System Bus Reset and Configuration Timings31Power-On Reset and Configuration Timings31System Bus Reset and Configuration Timings31Power-On Reset and Configuration Timings31Signal Quality32Test Timings (Boundary Scan)32Test Reset Timings32Signal Quality32Test Timings (Boundary Scan)32Test Reset Timings32System Bus Clock Signal Quality Specifications33AGTL+ Signal Quality Specifications33BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins33BCLK Signal Quality Specifications for Simulation at the Processor Core33System Bus Clock Signal Quality Specifications33AGTL+ Signal Quality Specifications33BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins33BCLK Signal Quality Specifications for Simulation at the Processor Core 1333.2.1 AGTL+ Ringback Tolerance Specifications343.2.2 AGTL+ Overshoot/Undershoot Guidelines34Low to High AGTL+ Receiver Ringback Tolerance34Core343.2.1 AGTL+ Ringback Tolerance Specifications343.2.2 AGTL+ Overshoot/Undershoot Guidelines34Low to High AGTL+ Receiver Ringback Tolerance34Non-AGTL+ Signal Quality Specifications353.3.1 2.5 V Tolerant Buffer Overshoot/Undershoot Guidelines353.3.2 2.5 V Tolerant Buffer Ringback Specification35Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback35AGTL+ Overshoot/Undershoot Guidelines at the Processor Core35Non-AGTL+ Signal Quality Specifications353.3.1 2.5 V Tolerant Buffer Overshoot/Undershoot Guidelines353.3.2 2.5 V Tolerant Buffer Ringback Specification35Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback35AGTL+ Overshoot/Undershoot Guidelines at the Processor Core353.3.3 2.5 V Tolerant Buffer Settling Limit Guideline36Processor Features36Functional Redundancy Checking Mode36Processor Core363.3.3 2.5 V Tolerant Buffer Settling Limit Guideline36Processor Features36Functional Redundancy Checking Mode36Low Power States and Clock Control374.2.1 Normal State— State 1374.2.2 Auto Halt Power Down State — State 237Low Power States and Clock Control374.2.1 Normal State— State 1374.2.2 Auto Halt Power Down State — State 2374.2.3 Stop-Grant State — State 338Stop Clock State Machine384.2.3 Stop-Grant State — State 338Stop Clock State Machine384.2.4 Halt/Grant Snoop State — State 4394.2.5 Sleep State — State 5394.2.6 Clock Control394.2.4 Halt/Grant Snoop State — State 4394.2.5 Sleep State — State 5394.2.6 Clock Control39System Management Bus (SMBus) Interface40Logical Schematic of SMBus Circuitry40System Management Bus (SMBus) Interface40Logical Schematic of SMBus Circuitry404.3.1 Processor Information ROM41Processor Information ROM Format414.3.1 Processor Information ROM41Processor Information ROM Format414.3.2 Scratch EEPROM424.3.2 Scratch EEPROM42SMBus Transactions43Thermal Sensor43Current Address Read SMBus Packet43Random Address Read SMBus Packet43Byte Write SMBus Packet434.3.4 Thermal Sensor43Current Address Read SMBus Packet43Random Address Read SMBus Packet43Byte Write SMBus Packet43Thermal Sensor Supported SMBus Transactions444.3.5 Thermal Sensor Supported SMBus Transactions44Write Byte SMBus Packet45Read Byte SMBus Packet45Send Byte SMBus Packet45Receive Byte SMBus Packet45ARA SMBus Packet45Command Byte Bit Assignments45Write Byte SMBus Packet45Read Byte SMBus Packet45Send Byte SMBus Packet45Receive Byte SMBus Packet45ARA SMBus Packet45Command Byte Bit Assignments45Thermal Sensor Registers464.3.6.1 Thermal Reference Registers464.3.6.2 Thermal Limit Registers464.3.6.3 Status Register464.3.6 Thermal Sensor Registers464.3.6.1 Thermal Reference Registers464.3.6.2 Thermal Limit Registers464.3.6.3 Status Register464.3.6.4 Configuration Register474.3.6.5 Conversion Rate Register47Thermal Sensor Status Register47Thermal Sensor Configuration Register474.3.6.4 Configuration Register474.3.6.5 Conversion Rate Register47Thermal Sensor Status Register47Thermal Sensor Configuration Register47SMBus Device Addressing48Thermal Sensor Conversion Rate Register48SMBus Device Addressing48Thermal Sensor Conversion Rate Register48Thermal Specifications and Design Considerations49Thermal Sensor SMBus Addressing on the Pentium® III Xeon™ Processor49Memory Device SMBus Addressing on the Pentium® III Xeon™ Processor49Thermal Specifications and Design Considerations49Thermal Sensor SMBus Addressing on the Pentium® III Xeon™ Processor49Memory Device SMBus Addressing on the Pentium® III Xeon™ Processor49Thermal Specifications505.1.1 Power Dissipation50Thermal Plate View50Thermal Specifications505.1.1 Power Dissipation50Thermal Plate View505.1.2 Plate Flatness Specification51Processor Thermal Analysis515.2.1 Thermal Solution Performance51Plate Flatness Reference51Thermal Design Power515.1.2 Plate Flatness Specification51Processor Thermal Analysis515.2.1 Thermal Solution Performance51Plate Flatness Reference51Thermal Design Power 1515.2.2 Thermal Plate to Heat Sink Interface Management Guide525.2.2 Thermal Plate to Heat Sink Interface Management Guide525.2.3 Measurements for Thermal Specifications535.2.3.1 Thermal Plate Temperature Measurement53Measurement Points535.2.3 Measurements for Thermal Specifications535.2.3.1 Thermal Plate Temperature Measurement535.2.3.2 Cover Temperature Measurement Guideline54Technique for Measuring TPLATE with 0° Angle Attachment54Technique for Measuring TPLATE with 90° Angle Attachment545.2.3.2 Cover Temperature Measurement Guideline54Technique for Measuring TPLATE with 0° Angle Attachment54Technique for Measuring TPLATE with 90° Angle Attachment54Mechanical Specifications55Placement55Mechanical Specifications55Isometric View of Pentium® III Xeon™ Processor S.E.C. Cartridge56Isometric View of Pentium® III Xeon™ Processor S.E.C. Cartridge56S.E.C. Cartridge Cooling Solution Attach Details (Notes follow Figure 27)57S.E.C. Cartridge Cooling Solution Attach Details (Notes follow Figure 27)57S.E.C. Cartridge Retention Enabling Details (Notes follow Figure 27)58S.E.C. Cartridge Retention Enabling Details (Notes follow Figure 27)58S.E.C. Cartridge Retention Enabling Details59S.E.C. Cartridge Retention Enabling Details59Weight60Cartridge to Connector Mating Details60Side View of Connector Mating Details60Weight60Cartridge to Connector Mating Details60Side View of Connector Mating Details60Top View of Cartridge Insertion Pressure Points61Front View of Connector Mating Details61Top View of Cartridge Insertion Pressure Points61Front View of Connector Mating Details61Pentium® III Xeon™ Processor Substrate Edge Finger Signal Listing62Signal Listing in Order by Pin Number62Pentium® III Xeon™ Processor Substrate Edge Finger Signal Listing62Signal Listing in Order by Pin Number62Signal Listing in Order by Pin Name66Signal Listing in Order by Pin Name66Boxed Processor Specifications71Introduction71Mechanical Specifications71Boxed Pentium® III Xeon™ Processor71Boxed Processor Specifications71Introduction71Mechanical Specifications71Boxed Pentium® III Xeon™ Processor71Side View Space Requirements for the Boxed Processor72Side View Space Requirements for the Boxed Processor727.2.1 Boxed Processor Heatsink Dimensions737.2.2 Boxed Processor Heatsink Weight737.2.3 Boxed Processor Retention Mechanism73Front View Space Requirements for the Boxed Processor73Boxed Processor Heatsink Dimensions737.2.1 Boxed Processor Heatsink Dimensions737.2.2 Boxed Processor Heatsink Weight737.2.3 Boxed Processor Retention Mechanism73Front View Space Requirements for the Boxed Processor73Boxed Processor Heatsink Dimensions73Thermal Specifications747.3.1 Boxed Processor Cooling Requirements747.3.2 Optional Auxiliary Fan Attachment74Thermal Specifications747.3.1 Boxed Processor Cooling Requirements747.3.2 Optional Auxiliary Fan Attachment74(Not Included with Boxed Processor)75(Fan Not Included)757.3.2.1 Clearance Recommendations for Auxiliary Fan76(Grommet Shown)76Side View Space Recommendation for the Auxiliary Fan767.3.2.1 Clearance Recommendations for Auxiliary Fan76Side View Space Recommendation for the Auxiliary Fan767.3.2.2 Fan Power Recommendations for Auxiliary Fan77Front View Space Recommendations for the Auxiliary Fan77Boxed Processor Fan/Heatsink Power Cable Connector Description777.3.2.2 Fan Power Recommendations for Auxiliary Fan77Front View Space Recommendations for the Auxiliary Fan77Boxed Processor Fan/Heatsink Power Cable Connector Description777.3.2.3 Thermal Evaluation for Auxiliary Fan78Integration Tools78In-Target Probe (ITP) for Pentium® III Xeon™ Processors78Fan/Heatsink Power and Signal Specifications787.3.2.3 Thermal Evaluation for Auxiliary Fan78Integration Tools78In-Target Probe (ITP) for Pentium® III Xeon™ Processors78Fan/Heatsink Power and Signal Specifications788.1.1 Primary Function798.1.2 Debug Port Connector Description79Hardware Components of an ITP798.1.1 Primary Function798.1.2 Debug Port Connector Description79Hardware Components of an ITP798.1.3 Debug Port Signal Descriptions80Debug Port Pinout Description and Requirements808.1.3 Debug Port Signal Descriptions80Debug Port Pinout Description and Requirements 1808.1.4 Debug Port Signal Notes82AGTL+ Signal Termination828.1.4 Debug Port Signal Notes82AGTL+ Signal Termination828.1.4.1 General Signal Quality Notes838.1.4.2 Signal Note: DBRESET#838.1.4.3 Signal Note: TDO and TDI838.1.4.4 Signal Note: TCK838.1.4.1 General Signal Quality Notes838.1.4.2 Signal Note: DBRESET#838.1.4.3 Signal Note: TDO and TDI838.1.4.4 Signal Note: TCK83TCK with Individual Buffering Scheme84TCK with Individual Buffering Scheme848.1.5 Using Boundary Scan to Communicate to the Processor85System Preferred Debug Port Layout858.1.5 Using Boundary Scan to Communicate to the Processor85System Preferred Debug Port Layout85Integration Tool (Logic Analyzer) Considerations86Appendix86Alphabetical Signals Reference869.1.1 A[35:03]# (I/O)869.1.2 A20M# (I)86Integration Tool (Logic Analyzer) Considerations86Appendix86Alphabetical Signals Reference869.1.1 A[35:03]# (I/O)86A20M# (I)869.1.3 ADS# (I/O)879.1.4 AERR# (I/O)879.1.5 AP[1:0]# (I/O)879.1.6 BCLK (I)879.1.7 BERR# (I/O)87ADS# (I/O)87AERR# (I/O)87AP[1:0]# (I/O)87BCLK (I)87BERR# (I/O)879.1.8 BINIT# (I/O)889.1.9 BNR# (I/O)889.1.10 BP[3:2]# (I/O)889.1.11 BPM[1:0]# (I/O)889.1.12 BPRI# (I)889.1.13 BR0# (I/O), BR[3:1]# (I)88BINIT# (I/O)88BNR# (I/O)88BP[3:2]# (I/O)88BPM[1:0]# (I/O)88BPRI# (I)88BR0# (I/O), BR[3:1]# (I)889.1.14 CPU_SENSE899.1.15 D[63:00]# (I/O)89BR[3:0]# Signals Rotating Interconnect, 4-Way System89BR[3:0]# Signals Rotating Interconnect, 2-Way System89Agent ID Configuration89CPU_SENSE89D[63:00]# (I/O)89BR[3:0]# Signals Rotating Interconnect, 4-Way System89BR[3:0]# Signals Rotating Interconnect, 2-Way System89Agent ID Configuration899.1.16 DBSY# (I/O)909.1.17 DEFER# (I)909.1.18 DEP[7:0]# (I/O)909.1.19 DRDY# (I/O)909.1.20 EMI909.1.21 FERR# (O)909.1.22 FLUSH# (I)90DBSY# (I/O)90DEFER# (I)90DEP[7:0]# (I/O)90DRDY# (I/O)90EMI90FERR# (O)90FLUSH# (I)909.1.23 FRCERR (I/O)919.1.24 HIT# (I/O), HITM# (I/O)919.1.25 IERR# (O)919.1.26 IGNNE# (I)91FRCERR (I/O)91HIT# (I/O), HITM# (I/O)91IERR# (O)91IGNNE# (I)919.1.27 INIT# (I)929.1.28 INTR - see LINT0929.1.29 LINT[1:0] (I)929.1.30 LOCK# (I/O)92INIT# (I)92INTR - see LINT092LINT[1:0] (I)92LOCK# (I/O)929.1.31 L2_SENSE939.1.32 NMI - See LINT1939.1.33 PICCLK (I)939.1.34 PICD[1:0] (I/O)939.1.35 PM[1:0]# (O)939.1.36 PRDY# (O)939.1.37 PREQ# (I)939.1.38 PWREN[1:0] (I)939.1.39 PWRGOOD (I)93L2_SENSE93NMI - See LINT193PICCLK (I)93PICD[1:0] (I/O)93PM[1:0]# (O)93PRDY# (O)93PREQ# (I)93PWREN[1:0] (I)93PWRGOOD (I)939.1.40 REQ[4:0]# (I/O)949.1.41 RESET# (I)94PWRGOOD Relationship at Power-On94REQ[4:0]# (I/O)94RESET# (I)94PWRGOOD Relationship at Power-On949.1.42 RP# (I/O)959.1.43 RS[2:0]# (I)959.1.44 RSP# (I)959.1.45 SA[2:0] (I)95RP# (I/O)95RS[2:0]# (I)95RSP# (I)95SA[2:0] (I)959.1.46 SELFSB[1:0] (I/O)969.1.47 SLP# (I)969.1.48 SMBALERT# (O)969.1.49 SMBCLK (I)969.1.50 SMBDAT (I/O)969.1.51 SMI# (I)96SELFSB[1:0] (I/O)96SLP# (I)96SMBALERT# (O)96SMBCLK (I)96SMBDAT (I/O)96SMI# (I)969.1.52 STPCLK# (I)979.1.53 TCK (I)979.1.54 TDI (I)979.1.55 TDO (O)979.1.56 TEST_25_A62 (I)979.1.57 TEST_VCC_CORE_XXX (I)979.1.58 THERMTRIP# (O)979.1.52 STPCLK# (I)979.1.53 TCK (I)979.1.54 TDI (I)979.1.55 TDO (O)979.1.56 TEST_25_A62 (I)979.1.57 TEST_VCC_CORE_XXX (I)979.1.58 THERMTRIP# (O)979.1.59 TMS (I)989.1.60 TRDY# (I)989.1.61 TRST# (I)989.1.62 VID_L2[4:0], VID_CORE[4:0](O)989.1.63 WP (I)98Signal Summaries98Output Signals989.1.59 TMS (I)989.1.60 TRDY# (I)989.1.61 TRST# (I)989.1.62 VID_L2[4:0], VID_CORE[4:0](O)989.1.63 WP (I)98Signal Summaries98Output Signals †98Input Signals199Input Signals 199I/O Signals (Single Driver)100I/O Signals (Multiple Driver)100I/O Signals (Single Driver)100I/O Signals (Multiple Driver)100Tamanho: 2 MBPáginas: 112Language: EnglishAbrir o manual
