Manual Do Utilizadoríndice analítico1. Block Diagram62. Signal List73. External Components84. General Description9Description of Blocks9Data Bus Buffers9Address and R/W Decode9Status and Data Quality Registers9Command, Mode, and Control Registers9Data Buffer9CRC Generator/Checker9FEC Generator/Checker9Interleave/De-Interleave Buffer9Frame Sync Detect94.1.10 Rx Input Amp104.1.11 RRC Low Pass Filter104.1.12 Tx Output Buffer114.1.13 Rx Level/Clock Extraction124.1.14 Clock Oscillator and Dividers12Modem - µC Interaction12Binary to Symbol Translation13Frame Structure14The Programmer’s View15Data Block Buffer15Command Register15Command Register B7: AQSC - Acquire Symbol Clock16Command Register B6: AQLEV - Acquire Receive Signal Levels16Command Register B5: CRC16Command Register B4: TXIMP - Tx Level/Impulse Shape16Command Register B3 - Reserved16Command Register B2, B1, B0: TASK16NULL: No effect18SFSH: Search for Frame Sync plus Header Block18RHB: Read Header Block184.5.2.10 RILB: Read 'Intermediate' or 'Last' Block184.5.2.11 SFS: Search for Frame Sync184.5.2.12 R4S: Read 4 Symbols194.5.2.13 T24S: Transmit 24 Symbols194.5.2.14 THB: Transmit Header Block194.5.2.15 TIB: Transmit Intermediate Block204.5.2.16 TLB: Transmit Last Block204.5.2.17 T4S: Transmit 4 Symbols204.5.2.18 RESET: Stop any current action204.5.2.19 Task Timing204.5.2.20 RRC Filter Delay21Control Register22Control Register B7, B6: CKDIV - Clock Division Ratio22Control Register B5, B4: FSTOL - Frame Sync Tolerance to Inexact Matches22Control Register B3, B2: LEVRES - Level Measurement Modes23Control Register B1, B0: PLLBW - Phase-Locked Loop Bandwidth Modes23Mode Register24Mode Register B7: IRQEN - IRQ Output Enable24Mode Register B6: INVSYM - Invert Symbols24Mode Register B5: TX/RX - Tx/Rx Mode24Mode Register B4: RXEYE - Show Rx Eye25Mode Register B3: PSAVE - Powersave25Mode Register B2, B1, B025Status Register26Status Register B7: IRQ - Interrupt Request26Status Register B6: BFREE - Data Block Buffer Free26Status Register B5: IBEMPTY - Interleave Buffer Empty26Status Register B4: DIBOVF - De-Interleave Buffer Overflow26Status Register B3: CRCERR - CRC Checksum Error27Status Register B2, B1, B027Data Quality Register27CRC, FEC, and Interleaving27Cyclic Redundancy Codes27CRC127CRC228Forward Error Correction28Interleaving28Transmitted Symbol Shape285. Application30Transmit Frame Example30Receive Frame Example33Clock Extraction and Level Measurement Systems36Supported Types of Systems36Clock and Level Acquisition Procedures with RF Carrier Detect36Clock and Level Acquisition Procedure without RF Carrier Detect36Automatic Acquisition Functions37AC Coupling37Radio Performance39Received Signal Quality Monitor406. Performance Specification41Electrical Performance41Absolute Maximum Ratings41Operating Limits41Operating Characteristics42Operating Characteristics Notes:42Timing43Typical Bit Error Rate45Packaging46Figure 1: Block Diagram6Figure 2: Recommended External Components8Figure 3: Typical Modem µC connections9Figure 4: Translation of Binary Data to Filtered 4-Level Symbols in Tx Mode10Figure 5: RRC Filter Frequency Response vs. Bit Rate (including the external RC filter R4/C5)11Figure 6: RRC Filter Frequency Response vs. Symbol Rate (including the external RC filter R4/C5)11Figure 7: Over-Air Signal Format14Figure 8: Alternative Frame Structures15Figure 9: Transmit Task Overlapping17Figure 10: Receive Task Overlapping17Figure 11: Transmit Task Timing Diagram21Figure 12: Receive Task Timing Diagram21Figure 13: RRC Low Pass Filter Delay21Figure 14: Ideal 'RXEYE' Signal25Figure 15: Typical Data Quality Reading vs S/N27Figure 16: Input Signal to RRC Filter in Tx Mode for TXIMP = 0 and 128Figure 17: Tx Signal Eye TXIMP = 029Figure 18: Tx Signal Eye TXIMP = 129Figure 19: Transmit Frame Example Flowchart, Main Program31Figure 20: Tx Interrupt Service Routine32Figure 21: Receive Frame Example Flowchart, Main Program34Figure 22: Rx Interrupt Service routine35Figure 23: Acquisition Sequence Timing36Figure 24: Effect of AC Coupling on BER (without FEC)37Figure 25: Decay Time - AC Coupling38Figure 26: Typical Connections between Radio and MX919B39Figure 27: Received Signal Quality Monitor Flowchart40Figure 28: µC Parallel Interface Timings44Figure 29: Typical Bit Error Rate With and Without FEC45Figure 30: 24-pin SOIC Mechanical Outline: Order as part no. MX919BDW46Figure 31: 24-pin SSOP Mechanical Outline: Order as part no. MX919BDS46Figure 32: 24-pin PLCC Mechanical Outline : Order as part no. MX919BLH47Figure 33: 24-pin PDIP Mechanical Outline: Order as part no. MX919BP47Tamanho: 900 KBPáginas: 47Language: EnglishAbrir o manual