Manual Do Utilizadoríndice analíticoContents51. Introduction131.1 Features131.2 Installation Guide151.3 Accessories172. Installation192.1 Unpacking192.2 Driver Installation202.3 Hardware Installation212.4 Device Setup & Configuration242.5 Device Testing273. Signal Connections313.1 Overview313.2 I/O Connector313.3 Analog Input Connections363.4 Analog Output Connections393.5 Field Wiring Considerations404. Software Overview414.1 Programming Choices414.2 DLL Driver Programming Roadmap425. Principles of Operation455.1 Analog Input Features455.2 Analog Output Features525.3 Digital I/O Features555.4 Counter/Timer Features566. Calibration676.1 VR Assignment676.2 A/D Calibration686.3 D/A Calibration696.4 Calibration Utility70Appendix A. Specification81Appendix B. Block Diagram85Appendix C. Screw-terminal Board87C. 1 Introduction87C. 2 Features87C. 3 Board Layout87C.4 Pin Assignment88C.5 Single-ended Connections89C.6 Differential Connections90Appendix D. Register Structure and Format91D.1 Overview91D.2 I/O Port Address Map91D.3 A/D Single Value Acquisition - Write BASE+095D.4 Channel and A/D data - Read BASE + 095D.5 A/D Channel Range Setting - Write BASE+296D.6 MUX Control - Write BASE+497D.7 A/D Control/Status Register - Write/Read BASE+699D.8 Clear interrupt and FIFO - Write BASE+8101D. 9 Interrupt and FIFO status - Read BASE+8102D.10 D/A control/status register - Write/Read BASE+A103D.11 D/A Channel 0/1 Data - Write BASE+C/E105D.12 82C54 Counter Chip 0 - Write/Read BASE+10 to 16106D.13 82C54 counter chip 1 - Write/Read BASE+18 to 1E107D.14 Counter gate and clock control/status - Write/ Read BASE+20 to 26108D.15 Digital I/O registers - Write/Read BASE+28111D.16 Digital I/O configuration registers - Write/Read BASE+2A112D.17 Calibration command registers - Write BASE+2C112D.18 D/A Channel Data for Continuous Output Operation Mode - Write BASE+30114Figures8Figure 2-1: The Setup Screen of Advantech Automation Software20Figure 2-2: Different options for Driver Setup21Figure 2-3: The device name listed on the Device Manager23Figure 2-4: The Advantech Device Installation utility program24Figure 2-5: The I/O Device Installation dialog box24Figure 2-6: The "Device(s) Found" dialog box25Figure 2-7: The Device Setting dialog box25Figure 2-8: The Device Name appearing on the list of devices box26Figure 2-9: Analog Input tab on the Device Test dialog box27Figure 2-10: Analog Input tab on the Device Test dialog box28Figure 2-11: Analog Output tab on the Device Test dialog box28Figure 2-12: Digital Input tab on the Device Test dialog box29Figure 2-13: Digital Output tab on the Device Test dialog box29Figure 2-14: Digital output tab on the Device Test dialog box30Figure 3-1: I/O connector pin assignments for the PCI-1712/1712L32Figure 3-2: Single-ended input channel connection36Figure 3-3: Differential input channel connection - ground reference signal source37Figure 3-4: Differential input channel connection - floating signal source38Figure 3-5: Analog output connections39Figure 5-1: Post-Trigger Acquisition Mode47Figure 5-2: Delay-Trigger Acquisition Mode47Figure 5-3: About-Trigger Acquisition Mode48Figure 5-4: Pre-Trigger Acquisition Mode49Figure 5-5: PCI-1712/1712L Sample Clock Source50Figure 5-6: Frequency measurement61Figure 6-1: PCI-1712/1712L VR1 & TP567Figure 6-2: Selecting the device you want to calibrate70Figure 6-3: Warning message before start calibration71Figure 6-4: Auto A/D Calibration Dialog Box71Figure 6-5: A/D Calibration Procedure 172Figure 6-6: A/D Calibration Procedure 272Figure 6-7: A/D Calibration Procedure 373Figure 6-8: A/D Calibration is finished73Figure 6-9: Range Selection in D/A Calibration74Figure 6-10: Calibrating D/A Channel 074Figure 6-11: Calibrating D/A Channel 175Figure 6-12: D/A Calibration is finished75Figure 6-13: Selecting Input Rage in Manual A/D Calibration panel76Figure 6-14: Adjusting registers77Figure 6-15: Selecting D/A Range and78Figure 6-16: Selecting D/A Range and Choosing Output Voltage78Figure 6-17: Adjusting registers79Figure C-1: PCLD-8712 board layout87Figure C-2: CN2 pin assignments for the PCLD-871288Tables10Table 3-1: I/O Connector Signal Description (Part 1)33Table 3-1: I/O Connector Signal Description (Part 2)34Table 3-1: I/O Connector Signal Description (Part 3)35Table 5-1: Gains and Analog Input Range45Table 5-2: Analog Input Data Format51Table 5-3: The corresponding Full Scale values for various Input Voltage Ranges51Table 5-4: Analog Output Data Format55Table 5-5: The corresponding Full Scale values for various Output Voltage Ranges55Table D-1: PCI-1712/1712L register format (Part 1)92Table D-1: PCI-1712/1712L register format (Part 2)93Table D-1: PCI-1712/1712L register format (Part 3)94Table D-2: Register for channel number and A/D data95Table D-3: Register for A/D channel range setting96Table D-4: Gain Codes for the PCI-1712/1712L97Table D-5: Register for multiplexer control97Table D-6: Register for A/D control/status99Table D-7: Analog Input Acquisition Mode100Table D-8: Register for clear interrupt and FIFO101Table D-9: Register for interrupt and FIFO status102Table D-10: Register for D/A control103Table D-11: Analog output operation mode104Table D-12: Register for D/A channel 0/1 data105Table D-13: Register for 82C54 counter chip 0106Table D-14: Register for 82C54 counter chip 1107Table D-15: Register for counter gate and clock control/status108Table D-16 : Table of Cn1 to Cn0 register108Table D-17: Table of Gn1 to Gn0 register109Table D-18: Table for CLK_SEL1 to CLK_SEL0 register111Table D-19: Register for Digital I/O111Table D-20: Register for digital I/O configuration112Table D-21: Register for digital I/O configuration112Table D-22: Register for calibration command112Table D-23: Calibration command113Table D-24: Register for D/A channel data114Tamanho: 3 MBPáginas: 114Language: EnglishAbrir o manual