Manuais de utilizador para Microchip Technology MA330031

índice analítico

• Operating Conditions

  1
• Core: 16-Bit dsPIC33E/PIC24E CPU

  1
• Clock Management

  1
• Power Management

  1
• High-Speed PWM

  1
• Advanced Analog Features

  1
• Timers/Output Compare/Input Capture

  1
• Communication Interfaces

  1
• Direct Memory Access (DMA)

  1
• Input/Output

  1
• Qualification and Class B Support

  1
• Debugger Development Support

  1
• dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X Product Families

  2
  • TABLE 1: dsPIC33EPXXXGP50X and PIC24EPXXXGP20X General Purpose Families

    2
  • TABLE 2: dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Motor Control Families

    3
  • Pin Diagrams

    5
  • Pin Diagrams (Continued)

    6
  • Pin Diagrams (Continued)

    7
  • Pin Diagrams (Continued)

    8
  • Pin Diagrams (Continued)

    9
  • Pin Diagrams (Continued)

    10
  • Pin Diagrams (Continued)

    11
  • Pin Diagrams (Continued)

    12
  • Pin Diagrams (Continued)

    13
  • Pin Diagrams (Continued)

    14
  • Pin Diagrams (Continued)

    15
  • Pin Diagrams (Continued)

    16
  • Pin Diagrams (Continued)

    17
  • Pin Diagrams (Continued)

    18
  • Pin Diagrams (Continued)

    19
  • Pin Diagrams (Continued)

    20
  • Pin Diagrams (Continued)

    21
  • Table of Contents

    22
  • Most Current Data Sheet

    23
  • Errata

    23
  • Customer Notification System

    23
  • Referenced Sources

    24
• 1.0 Device Overview

  25
  • FIGURE 1-1: dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X Block Diagram

    25
  • TABLE 1-1: Pinout I/O Descriptions

    26
• 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers and Microcontrollers

  29
  • 2.1 Basic Connection Requirements

    29
  • 2.2 Decoupling Capacitors

    29
    • FIGURE 2-1: Recommended Minimum connection

      30
  • 2.3 CPU Logic Filter Capacitor Connection (Vcap)

    30
  • 2.4 Master Clear (MCLR) Pin

    30
    • FIGURE 2-2: Example of MCLR Pin Connections

      30
  • 2.5 ICSP Pins

    31
  • 2.6 External Oscillator Pins

    31
    • FIGURE 2-3: Suggested Placement of the Oscillator Circuit

      31
  • 2.7 Oscillator Value Conditions on Device Start-up

    32
  • 2.8 Unused I/Os

    32
  • 2.9 Application Examples

    32
    • FIGURE 2-4: Boost Converter Implementation

      32
    • FIGURE 2-5: Single-Phase Synchronous Buck converter

      33
    • FIGURE 2-6: Multiphase Synchronous Buck converter

      33
    • FIGURE 2-7: Interleaved PFC

      34
    • FIGURE 2-8: BEMF voltage measured using the ADC Module

      34
• 3.0 CPU

  35
  • 3.1 Registers

    35
  • 3.2 Instruction Set

    35
  • 3.3 Data Space Addressing

    35
  • 3.4 Addressing Modes

    35
    • FIGURE 3-1: dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X CPU Block Diagram

      36
  • 3.5 Programmer’s Model

    37
    • TABLE 3-1: Programmer’s Model Register Descriptions

      37
    • FIGURE 3-2: Programmer’s Model

      38
  • 3.6 CPU Resources

    39
  • 3.7 CPU Control Registers

    40
    • Register 3-1: SR: CPU Status Register

      40
    • Register 3-2: CORCON: Core Control Register

      42
  • 3.8 Arithmetic Logic Unit (ALU)

    44
  • 3.9 DSP Engine (dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X Devices Only)

    44
    • TABLE 3-2: DSP Instructions Summary

      44
• 4.0 Memory Organization

  45
  • 4.1 Program Address Space

    45
    • FIGURE 4-1: Program Memory Map for dsPIC33EP32GP50X, dsPIC33EP32MC20X/50X and PIC24EP32GP/MC20X Devices

      45
    • FIGURE 4-2: Program Memory Map for dsPIC33EP64GP50X, dsPIC33EP64MC20X/50X and PIC24EP64GP/MC20X Devices

      46
    • FIGURE 4-3: Program Memory Map for dsPIC33EP128GP50X, dsPIC33EP128MC20X/50X and PIC24EP128GP/MC20X Devices

      47
    • FIGURE 4-4: Program Memory Map for dsPIC33EP256GP50X, dsPIC33EP256MC20X/50X and PIC24EP256GP/MC20X Devices

      48
    • FIGURE 4-5: Program Memory Map for dsPIC33EP512GP50X, dsPIC33EP512MC20X/50X and PIC24EP512GP/MC20X Devices

      49
    • FIGURE 4-6: Program Memory Organization

      50
  • 4.2 Data Address Space

    51
    • FIGURE 4-7: Data Memory Map for dsPIC33EP32MC20X/50X and dsPIC33EP32GP50X Devices

      52
    • FIGURE 4-8: Data Memory Map for dsPIC33EP64MC20X/50X and dsPIC33EP64GP50X Devices

      53
    • FIGURE 4-9: Data Memory Map for dsPIC33EP128MC20X/50X and dsPIC33EP128GP50X Devices

      54
    • FIGURE 4-10: Data Memory Map for dsPIC33EP256MC20X/50X and dsPIC33EP256GP50X Devices

      55
    • FIGURE 4-11: Data Memory Map for dsPIC33EP512MC20X/50X and dsPIC33EP512GP50X Devices

      56
    • FIGURE 4-12: Data Memory Map for PIC24EP32GP/MC20X/50X Devices

      57
    • FIGURE 4-13: Data Memory Map for PIC24EP64GP/MC20X/50X Devices

      58
    • FIGURE 4-14: Data Memory Map for PIC24EP128GP/MC20X/50X Devices

      59
    • FIGURE 4-15: Data Memory Map for PIC24EP256GP/MC20X/50X Devices

      60
    • FIGURE 4-16: Data Memory Map for PIC24EP512GP/MC20X/50X Devices

      61
  • 4.3 Memory Resources

    62
  • 4.4 Special Function Register Maps

    63
    • TABLE 4-1: CPU Core Register Map for dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X Devices Only

      63
    • TABLE 4-2: CPU Core Register Map for PIC24EPXXXGP/MC20X Devices Only

      65
    • TABLE 4-3: Interrupt Controller Register Map for PIC24EPXXXGP20X Devices Only

      66
    • TABLE 4-4: Interrupt Controller Register Map for PIC24EPXXXMC20X Devices Only

      67
    • TABLE 4-5: Interrupt Controller Register Map for dsPIC33EPXXXGP50X Devices Only

      69
    • TABLE 4-6: Interrupt Controller Register Map for dsPIC33EPXXXMC20X Devices Only

      71
    • TABLE 4-7: Interrupt Controller Register Map for dsPIC33EPXXXMC50X Devices Only

      73
    • TABLE 4-8: Timer1 through Timer5 Register Map

      75
    • TABLE 4-9: Input Capture 1 through Input Capture 4 Register Map

      76
    • TABLE 4-10: Output Compare 1 through Output Compare 4 Register Map

      77
    • TABLE 4-11: PTG Register Map

      78
    • TABLE 4-12: PWM Register Map for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only

      79
    • TABLE 4-13: PWM Generator 1 Register Map for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only

      79
    • TABLE 4-14: PWM Generator 2 Register Map for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only

      80
    • TABLE 4-15: PWM Generator 3 Register Map for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only

      80
    • TABLE 4-16: QEI1 Register Map for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only

      81
    • TABLE 4-17: I2C1 and I2C2 Register Map

      82
    • TABLE 4-18: UART1 and UART2 Register Map

      82
    • TABLE 4-19: SPI1 and SPI2 Register Map

      83
    • TABLE 4-20: ADC1 Register Map

      84
    • TABLE 4-21: ECAN1 Register Map When WIN (C1CTRL1<0>) = 0 or 1 FOR dsPIC33EPXXXMC/GP50X Devices Only

      85
    • TABLE 4-22: ECAN1 Register Map When WIN (C1CTRL1<0>) = 0 For dsPIC33EPXXXMC/GP50X Devices Only

      85
    • TABLE 4-23: ECAN1 Register Map When WIN (C1CTRL1<0>) = 1 For dsPIC33EPXXXMC/GP50X Devices Only

      86
    • TABLE 4-24: CRC Register Map

      88
    • TABLE 4-25: Peripheral Pin Select Output Register Map for dsPIC33EPXXXGP/MC202/502 and PIC24EPXXXGP/MC202 Devices Only

      88
    • TABLE 4-26: Peripheral Pin Select Output Register Map for dsPIC33EPXXXGP/MC203/503 and PIC24EPXXXGP/MC203 Devices Only

      88
    • TABLE 4-27: Peripheral Pin Select Output Register Map for dsPIC33EPXXXGP/MC204/504 and PIC24EPXXXGP/MC204 Devices Only

      89
    • TABLE 4-28: Peripheral Pin Select Output Register Map for dsPIC33EPXXXGP/MC206/506 and PIC24EPXXXGP/MC206 Devices Only

      89
    • TABLE 4-29: Peripheral Pin Select Input Register Map for PIC24EPXXXMC20X Devices Only

      90
    • TABLE 4-30: Peripheral Pin Select Input Register Map for PIC24EPXXXGP20X Devices Only

      90
    • TABLE 4-31: Peripheral Pin Select Input Register Map for dsPIC33EPXXXGP50X Devices Only

      91
    • TABLE 4-32: Peripheral Pin Select Input Register Map for dsPIC33EPXXXMC50X Devices Only

      91
    • TABLE 4-33: Peripheral Pin Select Input Register Map for dsPIC33EPXXXMC20X Devices Only

      92
    • TABLE 4-34: NVM Register Map

      93
    • TABLE 4-35: System Control Register Map

      93
    • TABLE 4-36: Reference Clock Register Map

      93
    • TABLE 4-37: PMD Register Map for PIC24EPXXXGP20X Devices Only

      94
    • TABLE 4-38: PMD Register Map for PIC24EPXXXMC20X Devices Only

      94
    • TABLE 4-39: PMD Register Map for dsPIC33EPXXXGP50X Devices Only

      95
    • TABLE 4-40: PMD Register Map for dsPIC33EPXXXMC50X Devices Only

      95
    • TABLE 4-41: PMD Register Map for dsPIC33EPXXXMC20X Devices Only

      96
    • TABLE 4-42: Op Amp/Comparator Register Map

      97
    • TABLE 4-43: CTMU Register Map

      97
    • TABLE 4-44: JTAG INTERFACE Register Map

      97
    • TABLE 4-45: DMAC Register Map

      98
    • TABLE 4-46: PORTA Register Map For PIC24EPXXXGP/MC206 and dsPIC33EPXXXGP/MC206/506 Devices Only

      99
    • TABLE 4-47: PORTB Register Map For PIC24EPXXXGP/MC206 and dsPIC33EPXXXGP/MC206/506 Devices Only

      99
    • TABLE 4-48: PORTC Register Map For PIC24EPXXXGP/MC206 and dsPIC33EPXXXGP/MC206/506 Devices Only

      99
    • TABLE 4-49: PORTD Register Map For PIC24EPXXXGP/MC206 and dsPIC33EPXXXGP/MC206/506 Devices Only

      100
    • TABLE 4-50: PORTE Register Map For PIC24EPXXXGP/MC206 and dsPIC33EPXXXGP/MC206/506 Devices Only

      100
    • TABLE 4-51: PORTF Register Map For PIC24EPXXXGP/MC206 and dsPIC33EPXXXGP/MC206/506 Devices Only

      100
    • TABLE 4-52: PORTG Register Map For PIC24EPXXXGP/MC206 and dsPIC33EPXXXGP/MC206/506 Devices Only

      101
    • TABLE 4-53: PORTA Register Map For PIC24EPXXXGP/MC204 and dsPIC33EPXXXGP/MC204/504 Devices Only

      102
    • TABLE 4-54: PORTB Register Map For PIC24EPXXXGP/MC204 and dsPIC33EPXXXGP/MC204/504 Devices Only

      102
    • TABLE 4-55: PORTC Register Map For PIC24EPXXXGP/MC204 and dsPIC33EPXXXGP/MC204/504 Devices Only

      102
    • TABLE 4-56: PORTA Register Map For PIC24EPXXXGP/MC203 and dsPIC33EPXXXGP/MC203/503 Devices Only

      103
    • TABLE 4-57: PORTB Register Map For PIC24EPXXXGP/MC203 and dsPIC33EPXXXGP/MC203/503 Devices Only

      103
    • TABLE 4-58: PORTC Register Map For PIC24EPXXXGP/MC203 and dsPIC33EPXXXGP/MC203/503 Devices Only

      103
    • TABLE 4-59: PORTA Register Map For PIC24EPXXXGP/MC202 and dsPIC33EPXXXGP/MC202/502 Devices Only

      104
    • TABLE 4-60: PORTB Register Map For PIC24EPXXXGP/MC202 and dsPIC33EPXXXGP/MC202/502 Devices Only

      104
    • EXAMPLE 4-1: Extended Data Space (EDS) Read Address Generation

      105
    • EXAMPLE 4-2: Extended Data Space (EDS) Write Address Generation

      106
    • EXAMPLE 4-3: Paged Data Memory Space

      107
    • TABLE 4-61: Overflow and Underflow Scenarios at Page 0, EDS and PSV Space Boundaries(2,3,4)

      108
    • FIGURE 4-17: EDS Memory Map

      109
    • TABLE 4-62: Data Memory Bus Arbiter Priority

      110
    • FIGURE 4-18: Arbiter Architecture

      110
    • FIGURE 4-19: CALL Stack Frame

      111
  • 4.5 Instruction Addressing Modes

    112
    • TABLE 4-63: Fundamental Addressing Modes Supported

      112
  • 4.6 Modulo Addressing (dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X Devices Only)

    114
    • FIGURE 4-20: Modulo Addressing Operation Example

      114
  • 4.7 Bit-Reversed Addressing (dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X Devices Only)

    115
    • FIGURE 4-21: Bit-Reversed Addressing Example

      116
    • TABLE 4-64: Bit-Reversed Addressing Sequence (16-Entry)

      116
  • 4.8 Interfacing Program and Data Memory Spaces

    117
    • TABLE 4-65: Program Space Address Construction

      117
    • FIGURE 4-22: Data Access from Program Space Address Generation

      117
    • FIGURE 4-23: Accessing Program Memory with Table Instructions

      118
• 5.0 Flash Program Memory

  119
  • 5.1 Table Instructions and Flash Programming

    119
    • FIGURE 5-1: Addressing for Table Registers

      119
  • 5.2 RTSP Operation

    120
  • 5.3 Programming Operations

    120
  • 5.4 Flash Memory Resources

    120
  • 5.5 Control Registers

    120
    • Register 5-1: NVMCON: Nonvolatile Memory (NVM) Control Register

      121
    • Register 5-2: NVMADRH: Nonvolatile Memory Address Register High

      122
    • Register 5-3: NVMADRL: Nonvolatile Memory Address Register Low

      122
    • Register 5-4: NVMKEY: Nonvolatile Memory Key

      122
• 6.0 Resets

  123
  • FIGURE 6-1: Reset System Block Diagram

    123
  • 6.1 Reset Resources

    124
    • Register 6-1: RCON: Reset Control Register(1)

      125
• 7.0 Interrupt Controller

  127
  • 7.1 Interrupt Vector Table

    127
  • 7.2 Reset Sequence

    127
    • FIGURE 7-1: dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X Interrupt Vector Table

      128
    • TABLE 7-1: Interrupt Vector Details

      129
  • 7.3 Interrupt Resources

    131
  • 7.4 Interrupt Control and Status Registers

    131
    • Register 7-1: SR: CPU Status Register(1)

      132
    • Register 7-2: CORCON: Core Control Register(1)

      133
    • Register 7-3: INTCON1: Interrupt Control Register 1

      134
    • Register 7-4: INTCON2: Interrupt Control Register 2

      136
    • Register 7-5: INTCON3: Interrupt Control Register 3

      137
    • Register 7-6: INTCON4: Interrupt Control Register 4

      137
    • Register 7-7: INTTREG: Interrupt Control and Status Register

      138
• 8.0 Direct Memory Access (DMA)

  139
  • FIGURE 8-1: DMA Controller Module

    139
  • TABLE 8-1: DMA Channel to Peripheral Associations

    140
  • FIGURE 8-2: DMA Controller Block Diagram

    141
  • 8.1 DMA Resources

    141
  • 8.2 DMAC Registers

    141
    • Register 8-1: DMAxCON: DMA Channel x Control Register

      142
    • Register 8-2: DMAxREQ: DMA Channel x IRQ Select Register

      143
    • Register 8-3: DMAxSTAH: DMA Channel x Start Address Register A (High)

      144
    • Register 8-4: DMAxSTAL: DMA Channel x Start Address Register A (Low)

      144
    • Register 8-5: DMAxSTBH: DMA Channel x Start Address Register B (High)

      145
    • Register 8-6: DMAxSTBL: DMA Channel x Start Address Register B (Low)

      145
    • Register 8-7: DMAxPAD: DMA Channel x Peripheral Address Register(1)

      146
    • Register 8-8: DMAxCNT: DMA Channel x Transfer Count Register(1)

      146
    • Register 8-9: DSADRH: DMA Most Recent RAM High Address Register

      147
    • Register 8-10: DSADRL: DMA Most Recent RAM Low Address Register

      147
    • Register 8-11: DMAPWC: DMA Peripheral Write Collision Status Register

      148
    • Register 8-12: DMARQC: DMA Request Collision Status Register

      149
    • Register 8-13: DMALCA: DMA Last Channel Active Status Register

      150
    • Register 8-14: DMAPPS: DMA Ping-Pong Status Register

      151
• 9.0 Oscillator Configuration

  153
  • FIGURE 9-1: Oscillator System Diagram

    153
  • 9.1 CPU Clocking System

    154
    • EQUATION 9-1: Device Operating Frequency

      154
    • FIGURE 9-2: PLL Block Diagram

      154
    • EQUATION 9-2: Fpllo Calculation

      154
    • EQUATION 9-3: Fvco Calculation

      154
    • TABLE 9-1: Configuration Bit Values for Clock Selection

      155
  • 9.2 Oscillator Resources

    155
  • 9.3 Oscillator Control Registers

    156
    • Register 9-1: OSCCON: Oscillator Control Register(1)

      156
    • Register 9-2: CLKDIV: Clock Divisor Register

      158
    • Register 9-3: PLLFBD: PLL Feedback Divisor Register

      160
    • Register 9-4: OSCTUN: FRC Oscillator Tuning Register

      161
    • Register 9-5: REFOCON: Reference Oscillator Control Register

      162
• 10.0 Power-Saving Features

  163
  • 10.1 Clock Frequency and Clock Switching

    163
  • 10.2 Instruction-Based Power-Saving Modes

    163
    • EXAMPLE 10-1: PWRSAV Instruction Syntax

      163
  • 10.3 Doze Mode

    165
  • 10.4 Peripheral Module Disable

    165
  • 10.5 Power-Saving Resources

    165
    • Register 10-1: PMD1: Peripheral Module Disable Control Register 1

      166
    • Register 10-2: PMD2: Peripheral Module Disable Control Register 2

      168
    • Register 10-3: PMD3: Peripheral Module Disable Control Register 3

      169
    • Register 10-4: PMD4: Peripheral Module Disable Control Register 4

      169
    • Register 10-5: PMD6: Peripheral Module Disable control Register 6

      170
    • Register 10-6: PMD7: Peripheral Module Disable control Register 7

      171
• 11.0 I/O Ports

  173
  • 11.1 Parallel I/O (PIO) Ports

    173
    • FIGURE 11-1: Block Diagram of a Typical Shared Port Structure

      173
  • 11.2 Configuring Analog and Digital Port Pins

    174
  • 11.3 Input Change Notification (ICN)

    174
    • EXAMPLE 11-1: Port Write/Read Example

      174
  • 11.4 Peripheral Pin Select (PPS)

    175
    • FIGURE 11-2: Remappable Input for U1RX

      176
    • EXAMPLE 11-2: Connecting IC1 to the HOME1 QEI1 Digital Filter Input on Pin 43 of the dsPIC33EPXXXMC206 Device

      176
    • TABLE 11-1: Selectable Input Sources (Maps Input to Function)

      177
    • TABLE 11-2: Input Pin Selection for Selectable Input sources

      178
    • FIGURE 11-3: Multiplexing Remappable Output for RPn

      180
    • TABLE 11-3: Output Selection for Remappable Pins (RPn)

      180
  • 11.5 I/O Helpful Tips

    181
  • 11.6 I/O Ports Resources

    182
  • 11.7 Peripheral Pin Select Registers

    183
    • Register 11-1: RPINR0: Peripheral Pin Select Input Register 0

      183
    • Register 11-2: RPINR1: Peripheral Pin Select Input Register 1

      184
    • Register 11-3: RPINR3: Peripheral Pin Select Input Register 3

      184
    • Register 11-4: RPINR7: Peripheral Pin Select Input Register 7

      185
    • Register 11-5: RPINR8: Peripheral Pin Select Input Register 8

      186
    • Register 11-6: RPINR11: Peripheral Pin Select Input Register 11

      187
    • Register 11-7: RPINR12: Peripheral Pin Select Input Register 12 (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)

      188
    • Register 11-8: RPINR14: Peripheral Pin Select Input Register 14 (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)

      189
    • Register 11-9: RPINR15: Peripheral Pin Select Input Register 15 (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)

      190
    • Register 11-10: RPINR18: Peripheral Pin Select Input Register 18

      191
    • Register 11-11: RPINR19: Peripheral Pin Select Input Register 19

      191
    • Register 11-12: RPINR22: Peripheral Pin Select Input Register 22

      192
    • Register 11-13: RPINR23: Peripheral Pin Select Input Register 23

      193
    • Register 11-14: RPINR26: Peripheral Pin Select Input Register 26 (dsPIC33EPXXXGP/MC50X Devices Only)

      193
    • Register 11-15: RPINR37: Peripheral Pin Select Input Register 37 (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)

      194
    • Register 11-16: RPINR38: Peripheral Pin Select Input Register 38 (dsPIC33EPXXXMC20X and PIC24EPXXXMC20X Devices Only)

      195
    • Register 11-17: RPINR39: Peripheral Pin Select Input Register 39 (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)

      196
    • Register 11-18: RPOR0: Peripheral Pin Select Output Register 0

      197
    • Register 11-19: RPOR1: Peripheral Pin Select Output Register 1

      197
    • Register 11-20: RPOR2: Peripheral Pin Select Output Register 2

      198
    • Register 11-21: RPOR3: Peripheral Pin Select Output Register 3

      198
    • Register 11-22: RPOR4: Peripheral Pin Select Output Register 4

      199
    • Register 11-23: RPOR5: Peripheral Pin Select Output Register 5

      199
    • Register 11-24: RPOR6: Peripheral Pin Select Output Register 6

      200
    • Register 11-25: RPOR7: Peripheral Pin Select Output Register 7

      200
    • Register 11-26: RPOR8: Peripheral Pin Select Output Register 8

      201
    • Register 11-27: RPOR9: Peripheral Pin Select Output Register 9

      201
• 12.0 Timer1

  203
  • TABLE 12-1: Timer Mode Settings

    203
  • FIGURE 12-1: 16-bit Timer1 Module Block Diagram

    203
  • 12.1 Timer1 Resources

    204
  • 12.2 Timer1 Control Register

    205
    • Register 12-1: T1CON: Timer1 Control Register

      205
• 13.0 Timer2/3 and Timer4/5

  207
  • FIGURE 13-1: Type B Timer block Diagram (x = 2 and 4)

    208
  • FIGURE 13-2: Type C Timer Block Diagram (x = 3 and 5)

    208
  • FIGURE 13-3: Type B/Type C Timer Pair Block Diagram (32-Bit Timer)

    209
  • 13.1 Timerx/y Resources

    209
  • 13.2 Timer Control Registers

    210
    • Register 13-1: TxCON: (TIMER2 and Timer4) Control Register

      210
    • Register 13-2: TyCON: (TIMER3 and TIMER5) Control Register

      211
• 14.0 Input Capture

  213
  • FIGURE 14-1: Input Capture x Module Block Diagram

    213
  • 14.1 Input Capture Resources

    214
  • 14.2 Input Capture Registers

    215
    • Register 14-1: ICxCON1: Input Capture X Control Register 1

      215
    • Register 14-2: ICxCON2: Input Capture X Control Register 2

      216
• 15.0 Output Compare

  219
  • FIGURE 15-1: Output Compare x Module Block Diagram

    219
  • 15.1 Output Compare Resources

    220
  • 15.2 Output Compare Control Registers

    221
    • Register 15-1: OCxCON1: Output Compare x Control Register 1

      221
    • Register 15-2: OCxCON2: Output Compare x Control Register 2

      223
• 16.0 High-Speed PWM Module (dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X Devices Only)

  225
  • 16.1 PWM Faults

    225
    • EXAMPLE 16-1: PWMx Write-Protected Register Unlock Sequence

      226
    • FIGURE 16-1: High-Speed PWMx Module Architectural Overview

      227
    • FIGURE 16-2: High-Speed PWMx Module Register Interconnection Diagram

      228
  • 16.2 PWM Resources

    229
  • 16.3 PWMx Control Registers

    230
    • Register 16-1: PTCON: PWMx Time Base Control Register

      230
    • Register 16-2: PTCON2: PWMx Primary Master Clock Divider Select Register 2

      232
    • Register 16-3: PTPER: PWMx Primary Master Time Base Period Register

      233
    • Register 16-4: SEVTCMP: PWMx Primary Special Event Compare Register

      233
    • Register 16-5: CHOP: PWMx Chop Clock Generator Register

      234
    • Register 16-6: MDC: PWMx Master Duty Cycle Register

      234
    • Register 16-7: PWMCONx: PWMx Control Register

      235
    • Register 16-8: PDCx: PWMx Generator Duty Cycle Register

      237
    • Register 16-9: PHASEx: PWMx Primary Phase-Shift Register

      237
    • Register 16-10: DTRx: PWMx Dead-Time Register

      238
    • Register 16-11: ALTDTRx: PWMx Alternate Dead-Time Register

      238
    • Register 16-12: TRGCONx: PWMx Trigger Control Register

      239
    • Register 16-13: IOCONx: PWMx I/O Control Register(2)

      240
    • Register 16-14: TRIGx: PWMx Primary Trigger Compare Value Register

      242
    • Register 16-15: FCLCONx: PWMx Fault Current-Limit Control Register(1)

      243
    • Register 16-16: LEBCONx: PWMx Leading-Edge Blanking Control Register

      245
    • Register 16-17: LEBDLYx: PWMx Leading-Edge Blanking Delay Register

      246
    • Register 16-18: AUXCONx: PWMx Auxiliary Control Register

      247
• 17.0 Quadrature Encoder Interface (QEI) Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)

  249
  • FIGURE 17-1: QEI Block Diagram

    250
  • 17.1 QEI Resources

    251
  • 17.2 QEI Control Registers

    252
    • Register 17-1: QEI1CON: QEI1 Control Register

      252
    • Register 17-2: QEI1IOC: QEI1 I/O Control Register

      254
    • Register 17-3: QEI1STAT: QEI1 Status register

      256
    • Register 17-4: POS1CNTH: Position Counter 1 High Word Register

      258
    • Register 17-5: POS1CNTL: Position Counter 1 Low Word Register

      258
    • Register 17-6: POS1HLD: Position Counter 1 Hold Register

      258
    • Register 17-7: VEL1CNT: Velocity Counter 1 Register

      259
    • Register 17-8: INDX1CNTH: Index Counter 1 High Word Register

      259
    • Register 17-9: INDX1CNTL: Index Counter 1 Low Word Register

      259
    • Register 17-10: INDX1HLD: Index Counter 1 Hold Register

      260
    • Register 17-11: QEI1ICH: QEI1 Initialization/Capture High Word Register

      260
    • Register 17-12: QEI1ICL: QEI1 Initialization/Capture Low Word Register

      260
    • Register 17-13: QEI1LECH: qei1 Less Than or Equal Compare High Word Register

      261
    • Register 17-14: QEI1LECL: qei1 Less Than or Equal Compare Low Word Register

      261
    • Register 17-15: QEI1GECH: QEI1 Greater Than or Equal Compare High Word Register

      262
    • Register 17-16: QEI1GECL: QEI1 Greater Than or Equal Compare Low Word Register

      262
    • Register 17-17: INT1TMRH: Interval 1 Timer High Word Register

      263
    • Register 17-18: INT1TMRL: Interval 1 Timer Low Word Register

      263
    • Register 17-19: INT1HLDH: Interval 1 Timer Hold High Word Register

      264
    • Register 17-20: INT1HLDL: Interval 1 Timer Hold Low Word Register

      264
• 18.0 Serial Peripheral Interface (SPI)

  265
  • FIGURE 18-1: SPIx Module Block Diagram

    266
  • 18.1 SPI Helpful Tips

    267
  • 18.2 SPI Resources

    267
  • 18.3 SPIx Control Registers

    268
    • Register 18-1: SPIxSTAT: SPIx Status and Control Register

      268
    • Register 18-2: SPIxCON1: SPIx Control Register 1

      270
    • Register 18-3: SPIxCON2: SPIx Control Register 2

      272
• 19.0 Inter-Integrated Circuit™ (I2C™)

  273
  • FIGURE 19-1: I2Cx Block Diagram (x = 1 or 2)

    274
  • 19.1 I2C Resources

    275
  • 19.2 I2C Control Registers

    276
    • Register 19-1: I2CxCON: I2Cx Control Register

      276
    • Register 19-2: I2CxSTAT: I2Cx Status Register

      278
    • Register 19-3: I2CxMSK: I2Cx Slave Mode Address Mask Register

      280
• 20.0 Universal Asynchronous Receiver Transmitter (UART)

  281
  • FIGURE 20-1: UARTx Simplified Block Diagram

    281
  • 20.1 UART Helpful Tips

    282
  • 20.2 UART Resources

    282
  • 20.3 UARTx Control Registers

    283
    • Register 20-1: UxMODE: UARTx Mode Register

      283
    • Register 20-2: UxSTA: UARTx Status and Control Register

      285
• 21.0 Enhanced CAN (ECAN™) Module (dsPIC33EPXXXGP/ MC50X Devices Only)

  287
  • 21.1 Overview

    287
    • FIGURE 21-1: ECAN™ Module Block Diagram

      288
  • 21.2 Modes of Operation

    289
  • 21.3 ECAN Resources

    289
  • 21.4 ECAN Control Registers

    290
    • Register 21-1: CxCTRL1: ECANx CONTROL REGISTER 1

      290
    • Register 21-2: CxCTRL2: ECANx Control Register 2

      291
    • Register 21-3: CxVEC: ECANx Interrupt Code Register

      292
    • Register 21-4: CxFCTRL: ECANx FIFO Control Register

      293
    • Register 21-5: CxFIFO: ECANx FIFO Status Register

      294
    • Register 21-6: CxINTF: ECANx Interrupt Flag Register

      295
    • Register 21-7: CxINTE: ECANx Interrupt Enable Register

      297
    • Register 21-8: CxEC: ECANx Transmit/Receive Error Count Register

      298
    • Register 21-9: CxCFG1: ECANx Baud Rate Configuration Register 1

      298
    • Register 21-10: CxCFG2: ECANx Baud Rate Configuration Register 2

      299
    • Register 21-11: CxFEN1: ECANx Acceptance Filter Enable Register 1

      300
    • Register 21-12: CxBUFPNT1: ECANx Filter 0-3 Buffer Pointer Register 1

      300
    • Register 21-13: CxBUFPNT2: ECANx Filter 4-7 Buffer Pointer Register 2

      301
    • Register 21-14: CxBUFPNT3: ECANx Filter 8-11 Buffer Pointer Register 3

      301
    • Register 21-15: CxBUFPNT4: ECANx Filter 12-15 Buffer Pointer Register 4

      302
    • Register 21-16: CxRXFnSID: ECANx Acceptance Filter n Standard Identifier Register (n = 0-15)

      303
    • Register 21-17: CxRXFnEID: ECANx Acceptance Filter n Extended Identifier Register (n = 0-15)

      304
    • Register 21-18: CxFMSKSEL1: ECANx Filter 7-0 Mask Selection Register 1

      304
    • Register 21-19: CxFMSKSEL2: ECANx Filter 15-8 Mask Selection Register 2

      305
    • Register 21-20: CxRXMnSID: ECANx Acceptance Filter Mask n Standard Identifier Register (n = 0-2)

      306
    • Register 21-21: CxRXMnEID: ECANx Acceptance Filter Mask n Extended Identifier Register (n = 0-2)

      306
    • Register 21-22: CxRXFUL1: ECANx Receive Buffer Full Register 1

      307
    • Register 21-23: CxRXFUL2: ECANx Receive Buffer Full Register 2

      307
    • Register 21-24: CxRXOVF1: ECANx Receive Buffer Overflow Register 1

      308
    • Register 21-25: CxRXOVF2: ECANx Receive Buffer Overflow Register 2

      308
    • Register 21-26: CxTRmnCON: ECANx TX/RX Buffer mn Control Register (m = 0,2,4,6; n = 1,3,5,7)

      309
  • 21.5 ECAN Message Buffers

    310
• 22.0 Charge Time Measurement Unit (CTMU)

  315
  • FIGURE 22-1: CTMU Block Diagram

    316
  • 22.1 CTMU Resources

    316
  • 22.2 CTMU Control Registers

    317
    • Register 22-1: CTMUCON1: CTMU Control Register 1

      317
    • Register 22-2: CTMUCON2: CTMU Control Register 2

      318
    • Register 22-3: CTMUICON: CTMU Current Control Register

      319
• 23.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC)

  321
  • 23.1 Key Features

    321
    • FIGURE 23-1: ADC Module Block Diagram with Connection Options for ANx pins and Op Amps

      322
    • FIGURE 23-2: ADC Conversion Clock Period Block Diagram

      323
  • 23.2 ADC Helpful Tips

    324
  • 23.3 ADC Resources

    324
  • 23.4 ADC Control Registers

    325
    • Register 23-1: AD1CON1: ADC1 Control Register 1

      325
    • Register 23-2: AD1CON2: ADC1 Control Register 2

      327
    • Register 23-3: AD1CON3: ADC1 Control Register 3

      329
    • Register 23-4: AD1CON4: ADC1 Control Register 4

      330
    • Register 23-5: AD1CHS123: ADC1 Input Channel 1, 2, 3 Select Register

      331
    • Register 23-6: AD1CHS0: ADC1 Input Channel 0 Select Register

      333
    • Register 23-7: AD1CSSH: ADC1 Input Scan Select Register High(1)

      335
    • Register 23-8: AD1CSSL: ADC1 Input Scan Select Register Low(1,2)

      336
• 24.0 Peripheral Trigger Generator (PTG) Module

  337
  • 24.1 Module Introduction

    337
    • FIGURE 24-1: PTG Block Diagram

      338
  • 24.2 PTG Resources

    339
  • 24.3 PTG Control Registers

    340
    • Register 24-1: PTGCST: PTG control/Status Register

      340
    • Register 24-2: PTGCON: PTG control Register

      342
    • Register 24-3: PTGBTE: PTG Broadcast Trigger Enable Register(1,2)

      343
    • Register 24-4: PTGT0LIM: PTG Timer0 Limit Register(1)

      345
    • Register 24-5: PTGT1LIM: PTG Timer1 Limit Register(1)

      345
    • Register 24-6: PTGSDLIM: PTG Step Delay Limit Register(1,2)

      346
    • Register 24-7: PTGC0LIM: PTG Counter 0 Limit Register(1)

      346
    • Register 24-8: PTGC1LIM: PTG Counter 1 Limit Register(1)

      347
    • Register 24-9: PTGHOLD: PTG Hold Register(1)

      347
    • Register 24-10: PTGADJ: PTG Adjust Register(1)

      348
    • Register 24-11: PTGL0: PTG Literal 0 Register(1)

      348
    • Register 24-12: PTGQPTR: PTG Step Queue Pointer Register(1)

      349
    • Register 24-13: PTGQUEx: PTG Step Queue Register x (x = 0-7)(1,3)

      349
  • 24.4 Step Commands and Format

    350
    • TABLE 24-1: PTG Step Command Format

      350
    • TABLE 24-1: PTG STEP Command Format (continued)

      351
    • TABLE 24-1: PTG STEP Command Format (continued)

      352
    • TABLE 24-2: PTG Output Descriptions

      353
• 25.0 Op Amp/Comparator Module

  355
  • FIGURE 25-1: Op Amp/Comparator x Module Block Diagram (Modules 1, 2 and 3)

    355
  • FIGURE 25-2: Comparator Module Block Diagram (Module 4)

    356
  • FIGURE 25-3: Op Amp/Comparator Voltage Reference Block Diagram

    356
  • FIGURE 25-4: User-Programmable Blanking Function Block Diagram

    357
  • FIGURE 25-5: Digital Filter Interconnect Block Diagram

    357
  • 25.1 Op Amp Application Considerations

    358
    • FIGURE 25-6: Op Amp Configuration A

      358
  • 25.2 Op Amp/Comparator Resources

    359
    • FIGURE 25-7: Op Amp Configuration B

      359
  • 25.3 Op Amp/Comparator Registers

    360
    • Register 25-1: CMSTAT: Op Amp/Comparator Status Register

      360
    • Register 25-2: CMxCON: Comparator x Control Register (x = 1, 2 or 3)

      362
    • Register 25-3: CM4CON: Comparator 4 Control Register

      364
    • Register 25-4: CMxMSKSRC: Comparator x Mask Source Select Control Register

      366
    • Register 25-5: CMxMSKCON: Comparator x Mask Gating Control Register

      368
    • Register 25-6: CMxFLTR: Comparator x Filter Control Register

      370
    • Register 25-7: CVRCON: Comparator Voltage Reference Control Register

      371
• 26.0 Programmable Cyclic Redundancy Check (CRC) Generator

  373
  • FIGURE 26-1: CRC Block Diagram

    373
  • FIGURE 26-2: CRC Shift Engine Detail

    374
  • 26.1 Overview

    374
    • TABLE 26-1: CRC SETUP Examples FOR 16 and 32-bit polynomial

      374
  • 26.2 Programmable CRC Resources

    374
  • 26.3 Programmable CRC Registers

    375
    • Register 26-1: CRCCON1: CRC Control Register 1

      375
    • Register 26-2: CRCCON2: CRC Control Register 2

      376
    • Register 26-3: CRCXORH: CRC XOR Polynomial HIGH Register

      377
    • Register 26-4: CRCXORL: CRC XOR Polynomial Low Register

      377
• 27.0 Special Features

  379
  • 27.1 Configuration Bits

    379
    • TABLE 27-1: Configuration Byte Register Map

      380
    • TABLE 27-2: Configuration Bits Description

      381
    • Register 27-1: DEVID: Device ID Register

      383
    • Register 27-2: DEVREV: Device Revision Register

      383
  • 27.2 User ID Words

    384
    • TABLE 27-3: User ID Words Register Map

      384
  • 27.3 On-Chip Voltage Regulator

    384
    • FIGURE 27-1: Connections for the On-Chip Voltage Regulator(1,2,3)

      384
  • 27.4 Brown-out Reset (BOR)

    384
  • 27.5 Watchdog Timer (WDT)

    385
    • FIGURE 27-2: WDT Block diagram

      385
  • 27.6 JTAG Interface

    386
  • 27.7 In-Circuit Serial Programming

    386
  • 27.8 In-Circuit Debugger

    386
  • 27.9 Code Protection and CodeGuard™ Security

    386
• 28.0 Instruction Set Summary

  387
  • TABLE 28-1: Symbols used in Opcode Descriptions

    388
  • TABLE 28-2: Instruction Set Overview

    390
• 29.0 Development Support

  397
  • 29.1 MPLAB X Integrated Development Environment Software

    397
  • 29.2 MPLAB XC Compilers

    398
  • 29.3 MPASM Assembler

    398
  • 29.4 MPLINK Object Linker/ MPLIB Object Librarian

    398
  • 29.5 MPLAB Assembler, Linker and Librarian for Various Device Families

    398
  • 29.6 MPLAB X SIM Software Simulator

    399
  • 29.7 MPLAB REAL ICE In-Circuit Emulator System

    399
  • 29.8 MPLAB ICD 3 In-Circuit Debugger System

    399
  • 29.9 PICkit 3 In-Circuit Debugger/ Programmer

    399
  • 29.10 MPLAB PM3 Device Programmer

    399
  • 29.11 Demonstration/Development Boards, Evaluation Kits and Starter Kits

    400
  • 29.12 Third-Party Development Tools

    400
• 30.0 Electrical Characteristics

  401
  • 30.1 DC Characteristics

    402
    • TABLE 30-1: Operating MIPS vs. Voltage

      402
    • TABLE 30-2: Thermal Operating Conditions

      402
    • TABLE 30-3: Thermal Packaging Characteristics

      402
    • TABLE 30-4: DC Temperature and Voltage specifications

      403
    • TABLE 30-5: Filter Capacitor (Cefc) Specifications

      403
    • TABLE 30-6: DC Characteristics: Operating Current (Idd)

      404
    • TABLE 30-7: DC Characteristics: Idle Current (iidle)

      405
    • TABLE 30-8: DC Characteristics: Power-Down Current (Ipd)

      406
    • TABLE 30-9: DC Characteristics: Watchdog Timer Delta Current (DIwdt)(1)

      407
    • TABLE 30-10: DC Characteristics: doze Current (Idoze)

      407
    • TABLE 30-11: DC Characteristics: I/O Pin Input Specifications

      408
    • TABLE 30-12: DC Characteristics: I/O Pin Output Specifications

      411
    • TABLE 30-13: Electrical Characteristics: BOR

      411
    • TABLE 30-14: DC Characteristics: Program Memory

      412
  • 30.2 AC Characteristics and Timing Parameters

    413
    • TABLE 30-15: Temperature and Voltage Specifications – AC

      413
    • FIGURE 30-1: Load Conditions for Device Timing Specifications

      413
    • TABLE 30-16: Capacitive Loading Requirements on Output Pins

      413
    • FIGURE 30-2: External Clock Timing

      414
    • TABLE 30-17: External Clock Timing Requirements

      414
    • TABLE 30-18: PLL Clock Timing Specifications

      415
    • TABLE 30-19: Internal FRC Accuracy

      415
    • TABLE 30-20: Internal LPRC accuracy

      415
    • FIGURE 30-3: I/O Timing Characteristics

      416
    • TABLE 30-21: I/O Timing Requirements

      416
    • FIGURE 30-4: BOR and Master Clear Reset Timing Characteristics

      416
    • TABLE 30-22: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer Timing Requirements

      417
    • FIGURE 30-5: Timer1-Timer5 External Clock Timing Characteristics

      418
    • TABLE 30-23: Timer1 External Clock Timing Requirements(1)

      418
    • TABLE 30-24: Timer2 and Timer4 (Type B Timer) External Clock Timing Requirements

      419
    • TABLE 30-25: Timer3 and Timer5 (Type C Timer) External Clock Timing Requirements

      419
    • FIGURE 30-6: INPUT CAPTURE x (ICx) TIMING Characteristics

      420
    • Table 30-26: Input Capture x Module Timing Requirements

      420
    • FIGURE 30-7: Output Compare x Module (OCx) Timing Characteristics

      421
    • TABLE 30-27: Output Compare x Module timing requirements

      421
    • FIGURE 30-8: OCx/PWMx Module Timing Characteristics

      421
    • TABLE 30-28: OCx/PWMx MODE Timing Requirements

      421
    • FIGURE 30-9: High-Speed PWMx Module Fault Timing Characteristics (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)

      422
    • FIGURE 30-10: High-Speed PWMx Module Timing Characteristics (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)

      422
    • TABLE 30-29: High-Speed PWMx Module Timing Requirements (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)

      422
    • FIGURE 30-11: TimerQ (QEI Module) External Clock Timing Characteristics (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)

      423
    • TABLE 30-30: QEI module External Clock Timing Requirements (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)

      423
    • FIGURE 30-12: QEA/QEB Input Characteristics (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)

      424
    • TABLE 30-31: Quadrature Decoder Timing Requirements (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)

      424
    • FIGURE 30-13: QEI Module Index Pulse Timing Characteristics (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)

      425
    • TABLE 30-32: QEI INDEX PULSE Timing Requirements (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)

      425
    • TABLE 30-33: SPI2 Maximum Data/Clock Rate Summary

      426
    • FIGURE 30-14: SPI2 MASTER MODE (Half-Duplex, Transmit Only, CKE = 0) TIMING CHARACTERISTICS

      426
    • FIGURE 30-15: SPI2 MASTER MODE (Half-Duplex, Transmit Only, CKE = 1) TIMING CHARACTERISTICS

      427
    • TABLE 30-34: SPI2 Master Mode (Half-Duplex, Transmit Only) Timing Requirements

      427
    • FIGURE 30-16: SPI2 MASTER MODE (Full-Duplex, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS

      428
    • TABLE 30-35: SPI2 Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements

      428
    • FIGURE 30-17: SPI2 MASTER MODE (Full-Duplex, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS

      429
    • TABLE 30-36: SPI2 Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements

      429
    • FIGURE 30-18: SPI2 SLAVE MODE (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS

      430
    • TABLE 30-37: SPI2 Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Timing Requirements

      431
    • FIGURE 30-19: SPI2 SLAVE MODE (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS

      432
    • TABLE 30-38: SPI2 Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Timing Requirements

      433
    • FIGURE 30-20: SPI2 SLAVE MODE (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS

      434
    • TABLE 30-39: SPI2 Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Timing Requirements

      435
    • FIGURE 30-21: SPI2 SLAVE MODE (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS

      436
    • TABLE 30-40: SPI2 Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Timing Requirements

      437
    • TABLE 30-41: SPI1 Maximum Data/Clock Rate Summary

      438
    • FIGURE 30-22: SPI1 MASTER MODE (Half-Duplex, Transmit Only, CKE = 0) TIMING CHARACTERISTICS

      438
    • FIGURE 30-23: SPI1 MASTER MODE (Half-Duplex, Transmit Only, CKE = 1) TIMING CHARACTERISTICS

      439
    • TABLE 30-42: SPI1 Master Mode (Half-Duplex, Transmit Only) Timing Requirements

      439
    • FIGURE 30-24: SPI1 MASTER MODE (Full-Duplex, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS

      440
    • TABLE 30-43: SPI1 Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements

      440
    • FIGURE 30-25: SPI1 MASTER MODE (Full-Duplex, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS

      441
    • TABLE 30-44: SPI1 Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements

      441
    • FIGURE 30-26: SPI1 SLAVE MODE (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS

      442
    • TABLE 30-45: SPI1 Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Timing Requirements

      443
    • FIGURE 30-27: SPI1 SLAVE MODE (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS

      444
    • TABLE 30-46: SPI1 Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Timing Requirements

      445
    • FIGURE 30-28: SPI1 SLAVE MODE (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS

      446
    • TABLE 30-47: SPI1 Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Timing Requirements

      447
    • FIGURE 30-29: SPI1 SLAVE MODE (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS

      448
    • TABLE 30-48: SPI1 Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Timing Requirements

      449
    • FIGURE 30-30: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)

      450
    • FIGURE 30-31: I2Cx Bus Data Timing Characteristics (Master mode)

      450
    • TABLE 30-49: I2Cx Bus Data Timing Requirements (Master Mode)

      451
    • FIGURE 30-32: I2Cx Bus Start/Stop Bits Timing Characteristics (slave mode)

      452
    • FIGURE 30-33: I2Cx Bus Data Timing Characteristics (slave mode)

      452
    • TABLE 30-50: I2Cx Bus Data Timing Requirements (Slave Mode)

      453
    • FIGURE 30-34: ECANx Module I/O Timing Characteristics

      454
    • TABLE 30-51: ECANx Module I/O Timing Requirements

      454
    • FIGURE 30-35: UARTx Module I/O Timing Characteristics

      454
    • TABLE 30-52: UARTx Module I/O Timing Requirements

      454
    • TABLE 30-53: Op Amp/Comparator Specifications

      455
    • TABLE 30-54: Op Amp/Comparator Voltage Reference Settling Time Specifications

      457
    • TABLE 30-55: Op Amp/Comparator Voltage Reference Specifications

      457
    • TABLE 30-56: CTMU Current Source Specifications

      458
    • TABLE 30-57: ADC Module Specifications

      459
    • TABLE 30-58: ADC Module Specifications (12-bit Mode)

      460
    • TABLE 30-59: ADC Module Specifications (10-bit Mode)

      461
    • FIGURE 30-36: ADC Conversion (12-bit mode) Timing Characteristics (asam = 0, ssrc<2:0> = 000, SSRCG = 0)

      462
    • TABLE 30-60: ADC Conversion (12-bit Mode) Timing Requirements

      463
    • FIGURE 30-37: ADC Conversion (10-bit mode) Timing Characteristics (chps<1:0> = 01, SIMSAM = 0, asam = 0, ssrc<2:0> = 000, SSRCG = 0)

      464
    • FIGURE 30-38: ADC Conversion (10-bit mode) Timing Characteristics (chps<1:0> = 01, SIMSAM = 0, asam = 1, ssrc<2:0> = 111, SSRCG = 0, SAMC<4:0> = 00010)

      464
    • TABLE 30-61: ADC CONVERSION (10-bit mode) TIMING Requirements

      465
    • TABLE 30-62: DMA Module Timing Requirements

      465
• 31.0 High-Temperature Electrical Characteristics

  467
  • 31.1 High-Temperature DC Characteristics

    468
    • TABLE 31-1: Operating MIPS vs. Voltage

      468
    • TABLE 31-2: Thermal Operating Conditions

      468
    • TABLE 31-3: DC Temperature and Voltage Specifications

      468
    • TABLE 31-4: DC Characteristics: Power-down Current (Ipd)

      469
    • TABLE 31-5: DC Characteristics: IDLE CURRENT (Iidle)

      469
    • TABLE 31-6: DC Characteristics: Operating Current (Idd)

      469
    • TABLE 31-7: DC Characteristics: Doze Current (Idoze)

      469
    • TABLE 31-8: DC Characteristics: I/O Pin Output Specifications

      470
  • 31.2 AC Characteristics and Timing Parameters

    471
    • TABLE 31-9: Temperature and Voltage Specifications – AC

      471
    • FIGURE 31-1: Load Conditions for Device Timing Specifications

      471
    • TABLE 31-10: PLL Clock Timing Specifications

      471
    • TABLE 31-11: Internal RC accuracy

      472
    • TABLE 31-12: ADC Module Specifications (12-bit Mode)

      473
    • TABLE 31-13: ADC Module Specifications (10-bit Mode)

      473
• 32.0 DC and AC Device Characteristics Graphs

  475
  • FIGURE 32-1: Voh – 4x Driver Pins

    475
  • FIGURE 32-2: Voh – 8x Driver Pins

    475
  • FIGURE 32-3: Vol – 4x Driver Pins

    475
  • FIGURE 32-4: Vol – 8x Driver Pins

    475
  • FIGURE 32-5: Typical Ipd Current @ Vdd = 3.3V

    476
  • FIGURE 32-6: Typical/Maximum Idd Current @ Vdd = 3.3V

    476
  • FIGURE 32-7: Typical Idoze Current @ Vdd = 3.3V

    476
  • FIGURE 32-8: Typical Iidle Current @ Vdd = 3.3V

    476
  • FIGURE 32-9: Typical FRC Frequency @ Vdd = 3.3V

    477
  • FIGURE 32-10: Typical LPRC Frequency @ Vdd = 3.3V

    477
  • FIGURE 32-11: Typical CTMU Temperature DIODE Forward Voltage

    477
• 33.0 Packaging Information

  479
  • 33.1 Package Marking Information

    479
  • 33.1 Package Marking Information (Continued)

    480
  • 33.1 Package Marking Information (Continued)

    481
  • 33.2 Package Details

    482
• Appendix A: Revision History

  507
  • TABLE A-1: Major Section Updates

    507
  • TABLE A-2: Major Section Updates

    509
  • TABLE A-3: Major Section Updates

    512
  • TABLE A-4: Major Section Updates

    513
  • TABLE A-5: Major Section Updates

    514
  • TABLE A-6: Major Section Updates

    516
• INDEX

  517
• The Microchip Web Site

  525
• Customer Change Notification Service

  525
• Customer Support

  525