Manuais de utilizador para Mitsubishi Electronics Q100UDEHCPU

índice analítico

• SAFETY PRECAUTIONS

  3
• CONDITIONS OF USE FOR THE PRODUCT

  9
• INTRODUCTION

  10
• CONTENTS

  12
• MANUALS

  14
• MANUAL PAGE ORGANIZATION

  16
• TERMS

  17
• CHAPTER 1 OVERVIEW

  20
• CHAPTER 2 CONCEPT OF MULTIPLE CPU SYSTEM

  26
  • 2.1 CPU Numbers

    26
  • 2.2 I/O Number Assignment

    29
    • 2.2.1 I/O numbers of I/O modules and intelligent function modules

      29
    • 2.2.2 I/O numbers of CPU modules

      32
• CHAPTER 3 SYSTEM CONFIGURATION

  33
  • 3.1 System Using Basic Model QCPU as CPU No.1

    34
    • 3.1.1 Available CPU modules, base units, power supply modules, and extension cables

      34
    • 3.1.2 CPU module combinations and mounting positions

      39
    • 3.1.3 Available I/O modules and intelligent function modules

      42
  • 3.2 System Using High Performance Model QCPU or Process CPU as CPU No.1

    43
    • 3.2.1 Available CPU modules, base units, power supply modules, and extension cables

      43
    • 3.2.2 CPU module combinations and mounting positions

      49
    • 3.2.3 Available I/O modules and intelligent function modules

      53
  • 3.3 System Using Universal Model QCPU as CPU No.1

    55
    • 3.3.1 Available CPU modules, base units, power supply modules, and extension cables

      55
    • 3.3.2 CPU module combinations and mounting positions

      62
    • 3.3.3 Available I/O modules and intelligent function modules

      66
  • 3.4 Applicable Software

    67
  • 3.5 Precautions for System Configuration

    70
• CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM

  77
  • 4.1 Procedure Before Operation

    77
  • 4.2 Operation Settings

    79
    • 4.2.1 System configuration example

      81
    • 4.2.2 Parameter settings

      82
  • 4.3 Program Examples for Communications by Auto Refresh

    89
    • 4.3.1 Program examples for Basic model QCPU, High Performance model QCPU, and Process CPU

      89
    • 4.3.2 Program examples for Universal model QCPU

      95
  • 4.4 Clock Data

    101
    • 4.4.1 Clock data of CPU modules

      101
    • 4.4.2 Clock data of intelligent function modules

      102
  • 4.5 Resetting a Multiple CPU System

    103
  • 4.6 System Operation When a Stop Error Occurs

    104
• CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES

  106
  • 5.1 Access to Controlled Modules

    106
  • 5.2 Access to Non-controlled Modules

    106
    • 5.2.1 Loading input (X) data

      107
    • 5.2.2 Loading output (Y) data

      109
    • 5.2.3 Output to output modules and intelligent function modules

      111
    • 5.2.4 Access to the intelligent function module buffer memory

      112
    • 5.2.5 Access using the link direct device

      113
  • 5.3 Access From a Programming Tool

    114
  • 5.4 Accessible QCPUs when GOT is connected

    117
• CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES

  118
  • 6.1 Communications Using the CPU Shared Memory

    120
    • 6.1.1 Communications by auto refresh (using the auto refresh area)

      124
    • 6.1.2 Communications by auto refresh (using the multiple CPU high speed transmission area)

      137
    • 6.1.3 Communications by programs using the CPU shared memory

      152
    • 6.1.4 Communications among CPU modules when an error is detected

      161
  • 6.2 Control Directions from QCPU to Motion CPU

    162
  • 6.3 Communications Among CPU Modules By Dedicated Instructions

    164
    • 6.3.1 Reading/writing device data from/to Motion CPU

      164
    • 6.3.2 Starting interrupt programs from QCPU to C Controller module/PC CPU module

      166
    • 6.3.3 Reading/writing device data between QCPUs

      167
  • 6.4 Multiple CPU Synchronous Interrupt

    168
  • 6.5 Multiple CPU synchronous startup

    170
• APPENDICES

  172
  • Appendix 1 Parameters for a Multiple CPU System

    172
    • Appendix 1.1 List of parameters

      174
  • Appendix 2 Comparison with a Single CPU System

    177
  • Appendix 3 Precautions for Using AnS/A Series Modules

    190
  • Appendix 4 Processing Time

    194
    • Appendix 4.1 Concept of scan time

      194
    • Appendix 4.2 Factors that increase scan time

      196
    • Appendix 4.3 Reducing processing time

      202
• INDEX

  203
• REVISIONS

  206
• WARRANTY

  209