Manuais de utilizador para Samsung C8274X

índice analítico

• NOTIFICATION OF REVISIONS

  3
• Table of Contents

  8
• List of Figures

  13
• List of Tables

  17
• List of Programming Tips

  19
• List of Register Descriptions

  20
• List of Instruction Descriptions

  21
• 1 PRODUCT OVERVIEW

  23
  • S3C8-SERIES MICROCONTROLLERS

    23
  • S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER

    23
  • FLASH

    23
  • FEATURES

    24
  • BLOCK DIAGRAM

    25
  • PIN ASSIGNMENT

    26
  • PIN DESCRIPTIONS

    28
  • PIN CIRCUITS

    30
  • Figure 1-1. Block Diagram

    25
  • Figure 1-2. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Assignments (64-QFP-1420F)

    26
  • Figure 1-3. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Assignments (64-LQFP-1010)

    27
  • Figure 1-4. Pin Circuit Type A

    30
  • Figure 1-5. Pin Circuit Type B (nRESET)

    30
  • Figure 1-6. Pin Circuit Type E-4 (P0, P1)

    30
  • Figure 1-7. Pin Circuit Type H-4

    31
  • Figure 1-8. Pin Circuit Type H-8 (P2.1 P2.7, P3)

    31
  • Figure 1-9. Pin Circuit Type H-9 (P4, P5, P6)

    32
  • Figure 1-10. Pin Circuit Type H-10 (P2.0)

    33
  • Table 1-1. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Descriptions

    28
• 2 ADDRESS SPACES

  34
  • OVERVIEW

    34
  • PROGRAM MEMORY (ROM)

    35
    • SMART OPTION

      36
  • REGISTER ARCHITECTURE

    38
    • REGISTER PAGE POINTER (PP)

      41
      • PROGRAMMING TIP Using the Page Pointer for RAM Clear (Page 0, Page 1)

        42
    • REGISTER SET 1

      43
    • REGISTER SET 2

      43
    • PRIME REGISTER SPACE

      44
    • WORKING REGISTERS

      45
    • USING THE REGISTER POINTS

      46
      • PROGRAMMING TIP Setting the Register Pointers

        46
      • PROGRAMMING TIP Using the RPs to Calculate the Sum of a Series of Registers

        47
  • REGISTER ADDRESSING

    48
    • COMMON WORKING REGISTER AREA (C0HCFH)

      50
      • PROGRAMMING TIP Addressing the Common Working Register Area

        51
    • 4-BIT WORKING REGISTER ADDRESSING

      51
    • 8-BIT WORKING REGISTER ADDRESSING

      53
  • SYSTEM AND USER STACK

    55
    • Programming TIP Standard Stack Operations Using PUSH and POP

      56
  • Figure 2-1. Program Memory Address Space

    35
  • Figure 2-2. Smart Option

    36
  • Figure 2-3. Internal Register File Organization (S3C8275X)

    39
  • Figure 2-4. Internal Register File Organization (S3C8278X/C8274X)

    40
  • Figure 2-5. Register Page Pointer (PP)

    41
  • Figure 2-6. Set 1, Set 2, Prime Area Register, and LCD Data Register Map

    44
  • Figure 2-7. 8-Byte Working Register Areas (Slices)

    45
  • Figure 2-8. Contiguous 16-Byte Working Register Block

    46
  • Figure 2-9. Non-Contiguous 16-Byte Working Register Block

    47
  • Figure 2-10. 16-Bit Register Pair

    48
  • Figure 2-11. Register File Addressing

    49
  • Figure 2-12. Common Working Register Area

    50
  • Figure 2-13. 4-Bit Working Register Addressing

    52
  • Figure 2-14. 4-Bit Working Register Addressing Example

    52
  • Figure 2-15. 8-Bit Working Register Addressing

    53
  • Figure 2-16. 8-Bit Working Register Addressing Example

    54
  • Figure 2-17. Stack Operations

    55
  • Table 2-1. S3C8275X Register Type Summary

    38
  • Table 2-2. S3C8278X/C8274X Register Type Summary

    38
• 3 ADDRESSING MODES

  57
  • OVERVIEW

    57
  • REGISTER ADDRESSING MODE (R)

    58
  • INDIRECT REGISTER ADDRESSING MODE (IR)

    59
  • INDEXED ADDRESSING MODE (X)

    63
  • DIRECT ADDRESS MODE (DA)

    66
  • INDIRECT ADDRESS MODE (IA)

    68
  • RELATIVE ADDRESS MODE (RA)

    69
  • IMMEDIATE MODE (IM)

    70
  • Figure 3-1. Register Addressing

    58
  • Figure 3-2. Working Register Addressing

    58
  • Figure 3-3. Indirect Register Addressing to Register File

    59
  • Figure 3-4. Indirect Register Addressing to Program Memory

    60
  • Figure 3-5. Indirect Working Register Addressing to Register File

    61
  • Figure 3-6. Indirect Working Register Addressing to Program or Data Memory

    62
  • Figure 3-7. Indexed Addressing to Register File

    63
  • Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset

    64
  • Figure 3-9. Indexed Addressing to Program or Data Memory

    65
  • Figure 3-10. Direct Addressing for Load Instructions

    66
  • Figure 3-11. Direct Addressing for Call and Jump Instructions

    67
  • Figure 3-12. Indirect Addressing

    68
  • Figure 3-13. Relative Addressing

    69
  • Figure 3-14. Immediate Addressing

    70
• 4 CONTROL REGISTERS

  71
  • BLDCON Battery Level Detector Control Register

    75
  • BTCON Basic Timer Control Register

    76
  • CLKCON System Clock Control Register

    77
  • CLOCON Clock Output Control Register

    78
  • EXTICONH External Interrupt Control Register (High Byte)

    79
  • EXTICONL External Interrupt Control Register (Low Byte)

    80
  • EXTIPND External Interrupt Pending Register

    81
  • FLAGS System Flags Register

    82
  • FMCON Flash Memory Control Register

    83
  • FMSECH Flash Memory Sector Address Register (High Byte)

    84
  • FMSECL Flash Memory Sector Address Register (Low Byte)

    84
  • FMUSR Flash Memory User Programming Enable Register

    85
  • IMR Interrupt Mask Register

    86
  • IPH Instruction Pointer (High Byte)

    87
  • IPL Instruction Pointer (Low Byte)

    87
  • IPR Interrupt Priority Register

    88
  • IRQ Interrupt Request Register

    89
  • LCON LCD Control Register

    90
  • OSCCON Oscillator Control Register

    91
  • P0CONH Port 0 Control Register (High Byte)

    92
  • P0CONL Port 0 Control Register (Low Byte)

    93
  • P0PUR Port 0 Pull-Up Control Register

    94
  • P1CONH Port 1 Control Register (High Byte)

    95
  • P1CONL Port 1 Control Register (Low Byte)

    96
  • P1PUR Port 1 Pull-up Control Register

    97
  • P2CONH Port 2 Control Register (High Byte)

    98
  • P2CONL Port 2 Control Register (Low Byte)

    99
  • P2PUR Port 2 Pull-up Control Register

    100
  • P3CONH Port 3 Control Register (High Byte)

    101
  • P3CONL Port 3 Control Register (Low Byte)

    102
  • P3PUR Port 3 Pull-up Control Register

    103
  • P4CONH Port 4 Control Register (High Byte)

    104
  • P4CONL Port 4 Control Register (Low Byte)

    105
  • P5CONH Port 5 Control Register (High Byte)

    106
  • P5CONL Port 5 Control Register (Low Byte)

    107
  • P6CON Port 6 Control Register

    108
  • PP Register Page Pointer

    109
  • RP0 Register Pointer 0

    110
  • RP1 Register Pointer 1

    110
  • SIOCON SIO Control Register

    111
  • SPH Stack Pointer (High Byte)

    112
  • SPL Stack Pointer (Low Byte)

    112
  • STPCON Stop Control Register

    113
  • SYM System Mode Register

    114
  • TACON Timer 1/A Control Register

    115
  • TBCON Timer B Control Register

    116
  • WTCON Watch Timer Control Register

    117
  • Figure 4-1. Register Description Format

    74
  • Table 4-1. Set 1 Registers

    71
  • Table 4-2. Set 1, Bank 0 Registers

    72
  • Table 4-3. Set 1, Bank 1 Registers

    73
• 5 INTERRUPT STRUCTURE

  118
  • OVERVIEW

    118
    • INTERRUPT TYPES

      119
    • S3C8275X/C8278X/C8274X INTERRUPT STRUCTURE

      120
    • INTERRUPT VECTOR ADDRESSES

      121
    • ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)

      123
    • SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS

      123
    • INTERRUPT PROCESSING CONTROL POINTS

      124
    • PERIPHERAL INTERRUPT CONTROL REGISTERS

      125
    • SYSTEM MODE REGISTER (SYM)

      126
    • INTERRUPT PRIORITY REGISTER (IPR)

      128
    • INTERRUPT MASK REGISTER (IMR)

      127
    • INTERRUPT PRIORITY REGISTER (IPR)

      128
    • INTERRUPT REQUEST REGISTER (IRQ)

      130
    • INTERRUPT PENDING FUNCTION TYPES

      131
      • Programming Tip How to clear an interrupt pending bit

        131
    • INTERRUPT SOURCE POLLING SEQUENCE

      132
    • INTERRUPT SERVICE ROUTINES

      132
    • GENERATING INTERRUPT VECTOR ADDRESSES

      133
    • NESTING OF VECTORED INTERRUPTS

      133
    • INSTRUCTION POINTER (IP)

      133
    • FAST INTERRUPT PROCESSING

      133
  • Figure 5-1. S3C8-Series Interrupt Types

    119
  • Figure 5-2. S3C8275X/C8278X/C8274X Interrupt Structure

    120
  • Figure 5-3. ROM Vector Address Area

    121
  • Figure 5-4. Interrupt Function Diagram

    124
  • Figure 5-5. System Mode Register (SYM)

    126
  • Figure 5-6. Interrupt Mask Register (IMR)

    127
  • Figure 5-7. Interrupt Request Priority Groups

    128
  • Figure 5-8. Interrupt Priority Register (IPR)

    129
  • Figure 5-9. Interrupt Request Register (IRQ)

    130
  • Table 5-1. Interrupt Vectors

    122
  • Table 5-2. Interrupt Control Register Overview

    123
  • Table 5-3. Interrupt Source Control and Data Registers

    125
• 6 INSTRUCTION SET

  135
  • OVERVIEW

    135
    • DATA TYPES

      135
    • REGISTER ADDRESSING

      135
    • ADDRESSING MODES

      135
    • FLAGS REGISTER (FLAGS)

      140
    • FLAG DESCRIPTIONS

      141
    • INSTRUCTION SET NOTATION

      142
    • CONDITION CODES

      146
    • INSTRUCTION DESCRIPTIONS

      147
  • Figure 6-1. System Flags Register (FLAGS)

    140
  • Table 6-1. Instruction Group Summary

    136
  • Table 6-2. Flag Notation Conventions

    142
  • Table 6-3. Instruction Set Symbols

    142
  • Table 6-4. Instruction Notation Conventions

    143
  • Table 6-5. Opcode Quick Reference

    144
  • Table 6-6. Condition Codes

    146
• 7 CLOCK CIRCUIT

  222
  • OVERVIEW

    222
    • SYSTEM CLOCK CIRCUIT

      222
    • MAIN OSCILLATOR CIRCUITS

      223
    • SUB OSCILLATOR CIRCUITS

      223
    • CLOCK STATUS DURING POWER-DOWN MODES

      224
    • SYSTEM CLOCK CONTROL REGISTER (CLKCON)

      225
    • CLOCK OUTPUT CONTROL REGISTER (CLOCON)

      226
    • OSCILLATOR CONTROL REGISTER (OSCCON)

      227
    • SWITCHING THE CPU CLOCK

      228
      • PROGRAMMING TIP Switching the CPU clock

        228
  • Figure 7-1. Crystal/Ceramic Oscillator (fx)

    223
  • Figure 7-2. External Oscillator (fx)

    223
  • Figure 7-3. RC Oscillator (fx)

    223
  • Figure 7-4. Crystal Oscillator (fxt)

    223
  • Figure 7-5. External Oscillator (fxt)

    223
  • Figure 7-6. System Clock Circuit Diagram

    224
  • Figure 7-7. System Clock Control Register (CLKCON)

    225
  • Figure 7-8. Clock Output Control Register (CLOCON)

    226
  • Figure 7-9. Clock Output Block Diagram

    226
  • Figure 7-10. Oscillator Control Register (OSCCON)

    227
  • Figure 7-11. STOP Control Register (STPCON)

    229
• 8 RESET and POWER-DOWN

  230
  • SYSTEM RESET

    230
    • OVERVIEW

      230
    • NORMAL MODE RESET OPERATION

      230
    • HARDWARE RESET VALUES

      231
  • POWER-DOWN MODES

    234
    • STOP MODE

      234
    • IDLE MODE

      235
  • Table 8-1. S3C8275X/C8278X/C8274X Set 1 Register and Values After RESET

    231
  • Table 8-2. S3C8275X/C8278X/C8274X Set 1, Bank 0 Register Values After RESET

    232
  • Table 8-3. S3C8275X/C8278X/C8274X Set 1, Bank 1 Register Values After RESET

    233
• 9 I/O PORTS

  236
  • OVERVIEW

    236
    • PORT DATA REGISTERS

      237
    • PORT 0

      238
    • PORT 1

      242
    • PORT 2

      246
    • PORT 3

      248
    • PORT 4

      250
    • PORT 5

      252
    • PORT 6

      254
  • Figure 9-1. S3C8275X/C8278X/C8274X I/O Port Data Register Format

    237
  • Figure 9-2. Port 0 High-Byte Control Register (P0CONH)

    239
  • Figure 9-3. Port 0 Low-Byte Control Register (P0CONL)

    239
  • Figure 9-4. Port 0 Pull-up Control Register (P0PUR)

    240
  • Figure 9-5. External Interrupt Control Register, Low Byte (EXTICONL)

    240
  • Figure 9-6. External Interrupt Pending Register (EXTIPND)

    241
  • Figure 9-7. Port 1 High-Byte Control Register (P1CONH)

    243
  • Figure 9-8. Port 1 Low-Byte Control Register (P1CONL)

    243
  • Figure 9-9. Port 1 Pull-up Control Register (P1PUR)

    244
  • Figure 9-10. External Interrupt Control Register, High Byte (EXTICONH)

    244
  • Figure 9-11. External Interrupt Control Register, Low Byte (EXTICONL)

    245
  • Figure 9-12. External Interrupt Pending Register (EXTIPND)

    245
  • Figure 9-13. Port 2 High-byte Control Register (P2CONH)

    246
  • Figure 9-14. Port 2 Low-byte Control Register (P2CONL)

    247
  • Figure 9-15. Port 2 Pull-up Control Register (P2PUR)

    247
  • Figure 9-16. Port 3 High Byte Control Register (P3CONH)

    248
  • Figure 9-17. Port 3 Low Byte Control Register (P3CONL)

    249
  • Figure 9-18. Port 3 Pull-up Control Register (P3PUR)

    249
  • Figure 9-19. Port 4 High-Byte Control Register (P4CONH)

    250
  • Figure 9-20. Port 4 Low-Byte Control Register (P4CONL)

    251
  • Figure 9-21. Port 5 High-Byte Control Register (P5CONH)

    252
  • Figure 9-22. Port 5 Low-Byte Control Register (P5CONL)

    253
  • Figure 9-23. Port 6 Control Register (P6CON)

    254
  • Table 9-1. S3C8275X/C8278X/C8274X Port Configuration Overview

    236
  • Table 9-2. Port Data Register Summary

    237
• 10 BASIC TIMER

  255
  • OVERVIEW

    255
    • BASIC TIMER CONTROL REGISTER (BTCON)

      256
    • BASIC TIMER FUNCTION DESCRIPTION

      257
  • Figure 10-1. Basic Timer Control Register (BTCON)

    256
  • Figure 10-2. Basic Timer Block Diagram

    258
• 11 TIMER 1

  259
  • ONE 16-BIT TIMER MODE (TIMER 1)

    259
    • OVERVIEW

      259
    • FUNCTION DESCRIPTION

      259
  • TWO 8-BIT TIMERS MODE (TIMER A and B)

    262
    • OVERVIEW

      262
    • FUNCTION DESCRIPTION

      262
  • Figure 11-1. Timer 1/A Control Register (TACON)

    260
  • Figure 11-2. Timer 1 Block Diagram (One 16-bit Mode)

    261
  • Figure 11-3. Timer 1/A Control Register (TACON)

    263
  • Figure 11-4. Timer B Control Register (TBCON)

    264
  • Figure 11-5. Timer A Block Diagram (Two 8-bit Timers Mode)

    265
  • Figure 11-6. Timer B Block Diagram (Two 8-bit Timers Mode)

    266
• 12 WATCH TIMER

  267
  • OVERVIEW

    267
    • WATCH TIMER CONTROL REGISTER (WTCON)

      268
    • WATCH TIMER CIRCUIT DIASGRAM

      269
  • Figure 12-1. Watch Timer Control Register (WTCON)

    268
  • Figure 12-2. Watch Timer Circuit Diagram

    269
• 13 LCD CONTROLLER/DRIVER

  270
  • OVERVIEW

    270
    • LCD CIRCUIT DIAGRAM

      271
    • LCD RAM ADDRESS AREA

      272
    • LCD CONTROL REGISTER (LCON)

      273
    • LCD VOLTAGE DIVIDING RESISTOR

      274
    • COMMON (COM) SIGNALS

      275
    • SEGMENT (SEG) SIGNALS

      275
  • Figure 13-1. LCD Function Diagram

    270
  • Figure 13-2. LCD Circuit Diagram

    271
  • Figure 13-3. LCD Display Data RAM Organization

    272
  • Figure 13-4. LCD Control Register (LCON)

    273
  • Figure 13-5. Internal Voltage Dividing Resistor Connection

    274
  • Figure 13-6. Select/No-Select Signals in Static Display Mode

    275
  • Figure 13-7. Select/No-Select Signal in 1/2 Duty, 1/2 Bias Display Mode

    276
  • Figure 13-8. Select/No-Select Signal in 1/3 Duty, 1/3 Bias Display Mode

    276
  • Figure 13-9. LCD Signals and Wave Forms Example in 1/4 Duty, 1/3 Bias Display Mode

    277
• 14 SERIAL I/O INTERFACE

  278
  • OVERVIEW

    278
    • PROGRAMMING PROCEDURE

      278
    • SIO CONTROL REGISTERS (SIOCON)

      279
    • SIO PRE-SCALER REGISTER (SIOPS)

      280
  • SIO BLOCK DIAGRAM

    280
    • SERIAL I/O TIMING DIAGRAM (SIO)

      281
  • Figure 14-1. Serial I/O Module Control Register (SIOCON)

    279
  • Figure 14-2. SIO Prescaler Register (SIOPS)

    280
  • Figure 14-3. SIO Functional Block Diagram

    280
  • Figure 14-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0)

    281
  • Figure 14-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)

    281
• 15 BATTERY LEVEL DETECTOR

  282
  • OVERVIEW

    282
    • BATTERY LEVEL DETECTOR CONTROL REGISTER (BLDCON)

      283
  • Figure 15-1. Block Diagram for Voltage Level Detect

    282
  • Figure 15-2. Battery Level Detect Circuit and Control Register

    283
  • Table 15-1. BLDCON Value and Detection Level

    283
• 16 EMBEDDED FLASH MEMORY INTERFACE

  284
  • OVERVIEW

    284
  • USER PROGRAM MODE

    285
    • FLASH MEMORY CONTROL REGISTERS (USER PROGRAM MODE)

      285
  • ISPTM (ON-BOARD PROGRAMMING) SECTOR

    288
  • SECTOR ERASE

    290
    • PROGRAMMING TIP Sector Erase

      291
  • PROGRAMMING

    292
    • PROGRAMMING TIP Program

      293
  • READING

    294
    • PROGRAMMING TIP Reading

      294
  • HARD LOCK PROTECTION

    295
    • PROGRAMMING TIP Hard Lock Protection

      295
  • Figure 16-1. Flash Memory Control Register (FMCON)

    285
  • Figure 16-2. Flash Memory User Programming Enable Register (FMUSR)

    286
  • Figure 16-3. Flash Memory Sector Address Register, High Byte (FMSECH)

    287
  • Figure 16-4. Flash Memory Sector Address Register, Low Byte (FMSECL)

    287
  • Figure 16-5. Program Memory Address Space

    288
  • Figure 16-6. Sector Configurations in User Program Mode

    290
  • Table 16-1. ISP Sector Size

    289
  • Table 16-2. Reset Vector Address

    289
• 17 ELECTRICAL DATA

  296
  • Figure 17-1. Stop Mode Release Timing When Initiated by an External Interrupt

    300
  • Figure 17-2. Stop Mode Release Timing When Initiated by a RESET

    301
  • Figure 17-3. Input Timing for External Interrupts

    302
  • Figure 17-4. Input Timing for RESET

    303
  • Figure 17-5. Serial Data Transfer Timing

    303
  • Figure 17-6. LVR (Low Voltage Reset) Timing

    304
  • Figure 17-7. Clock Timing Measurement at XIN

    306
  • Figure 17-8. Clock Timing Measurement at XTIN

    307
  • Figure 17-9. Operating Voltage Range

    308
  • Table 17-1. Absolute Maximum Ratings

    297
  • Table 17-2. D.C. Electrical Characteristics

    297
  • Table 17-3. Data Retention Supply Voltage in Stop Mode

    300
  • Table 17-4. Input/Output Capacitance

    301
  • Table 17-5. A.C. Electrical Characteristics

    302
  • Table 17-6. Battery Level Detector Electrical Characteristics

    304
  • Table 17-7. LVR (Low Voltage Reset) Electrical Characteristics

    304
  • Table 17-8. Main Oscillation Characteristics

    305
  • Table 17-9. Sub Oscillation Characteristics

    305
  • Table 17-10. Main Oscillation Stabilization Time

    306
  • Table 17-11. Sub Oscillation Stabilization Time

    307
  • Table 17-12. A.C. Electrical Characteristics for Internal Flash ROM

    308
• 18 MECHANICAL DATA

  309
  • Figure 18-1. 64-Pin QFP Package Dimensions (64-QFP-1420F)

    309
  • Figure 18-2. 64-Pin LQFP Package Dimensions (64-LQFP-1010)

    310
• 19 S3F8275X/F8278X/F8274X FLASH MCU

  311
  • OVERVIEW

    311
    • OPERATING MODE CHARACTERISTICS

      315
  • Figure 19-1. S3F8275X/F8278X/F8274X Pin Assignments (64-QFP-1420F)

    312
  • Figure 19-2. S3F8275X/F8278X/F8274X Pin Assignments (64-LQFP-1010)

    313
  • Figure 19-3. Operating Voltage Range

    317
  • Table 19-1. Descriptions of Pins Used to Read/Write the Flash ROM

    314
  • Table 19-2. Comparison of S3F8275X/F8278X/F8274X and S3C8275X/C8278X/C8274X Features

    314
  • Table 19-3. Operating Mode Selection Criteria

    315
  • Table 19-4. D.C. Electrical Characteristics

    316
• 20 DEVELOPMENT TOOLS

  318
  • OVERVIEW

    318
    • SHINE

      318
    • SAMA ASSEMBLER

      318
    • SASM88

      318
    • HEX2ROM

      318
    • TARGET BOARDS

      318
    • TB8275/8/4 TARGET BOARD

      320
    • SMDS2+ SELECTION (SAM8)

      323
    • IDLE LED

      323
    • STOP LED

      323
  • Figure 20-1. SMDS Product Configuration (SMDS2+)

    319
  • Figure 20-2. TB8275/8/4 Target Board Configuration

    320
  • Figure 20-3. 40-Pin Connectors (J101, J102) for TB8275/8/4

    324
  • Figure 20-4. S3E8270 Cables for 64-QFP Package

    324
  • Table 20-1. Power Selection Settings for TB8275/8/4

    321
  • Table 20-2. Main-clock Selection Settings for TB8275/8/4

    321
  • Table 20-3. Select Smart Option Source Setting for TB8275/8/4

    322
  • Table 20-4. Smart Option Switch Settings for TB8275/8/4

    322
  • Table 20-5. Device Selection Settings for TB8275/8/4

    323
  • Table 20-6. The SMDS2+ Tool Selection Setting

    323