Manuais de utilizador para Silicon Laboratories C8051F342

índice analítico

• 1. System Overview

  17
• 1.1. CIP-51™ Microcontroller Core

  21
• 1.1.1. Fully 8051 Compatible

  21
• 1.1.2. Improved Throughput

  21
• 1.1.3. Additional Features

  21
• 1.2. On-Chip Memory

  23
• 1.3. Universal Serial Bus Controller

  24
• 1.4. Voltage Regulator

  25
• 1.5. On-Chip Debug Circuitry

  25
• 1.6. Programmable Digital I/O and Crossbar

  26
• 1.7. Serial Ports

  27
• 1.8. Programmable Counter Array

  27
• 1.9. 10-Bit Analog to Digital Converter

  28
• 1.10.Comparators

  29
• 2. Absolute Maximum Ratings

  30
• 3. Global DC Electrical Characteristics

  31
• 4. Pinout and Package Definitions

  33
• 5. 10-Bit ADC (ADC0)

  41
• 5.1. Analog Multiplexer

  42
• 5.2. Temperature Sensor

  43
• 5.3. Modes of Operation

  45
• 5.3.1. Starting a Conversion

  45
• 5.3.2. Tracking Modes

  46
• 5.3.3. Settling Time Requirements

  47
• 5.4. Programmable Window Detector

  52
• 5.4.1. Window Detector In Single-Ended Mode

  54
• 5.4.2. Window Detector In Differential Mode

  55
• 6. Voltage Reference

  57
• 7. Comparators

  59
• 8. Voltage Regulator (REG0)

  69
• 8.1. Regulator Mode Selection

  69
• 8.2. VBUS Detection

  69
• 9. CIP-51 Microcontroller

  73
• 9.1. Instruction Set

  74
• 9.1.1. Instruction and CPU Timing

  74
• 9.1.2. MOVX Instruction and Program Memory

  75
• 9.2. Memory Organization

  79
• 9.2.1. Program Memory

  79
• 9.2.2. Data Memory

  80
• 9.2.3. General Purpose Registers

  80
• 9.2.4. Bit Addressable Locations

  80
• 9.2.5. Stack

  80
• 9.2.6. Special Function Registers

  81
• 9.2.7. Register Descriptions

  85
• 9.3. Interrupt Handler

  87
• 9.3.1. MCU Interrupt Sources and Vectors

  87
• 9.3.2. External Interrupts

  87
• 9.3.3. Interrupt Priorities

  88
• 9.3.4. Interrupt Latency

  88
• 9.3.5. Interrupt Register Descriptions

  89
• 9.4. Power Management Modes

  96
• 9.4.1. Idle Mode

  96
• 9.4.2. Stop Mode

  96
• 10. Prefetch Engine

  99
• 11. Reset Sources

  101
• 11.1.Power-On Reset

  102
• 11.2.Power-Fail Reset / VDD Monitor

  103
• 11.3.External Reset

  104
• 11.4.Missing Clock Detector Reset

  104
• 11.5.Comparator0 Reset

  104
• 11.6.PCA Watchdog Timer Reset

  104
• 11.7.Flash Error Reset

  104
• 11.8.Software Reset

  105
• 11.9.USB Reset

  105
• 12. Flash Memory

  109
• 12.1.Programming The Flash Memory

  109
• 12.1.1.Flash Lock and Key Functions

  109
• 12.1.2.Flash Erase Procedure

  109
• 12.1.3.Flash Write Procedure

  110
• 12.2.Non-volatile Data Storage

  111
• 12.3.Security Options

  111
• 13. External Data Memory Interface and On-Chip XRAM

  117
• 13.1.Accessing XRAM

  117
• 13.1.1.16-Bit MOVX Example

  117
• 13.1.2.8-Bit MOVX Example

  117
• 13.2.Accessing USB FIFO Space

  118
• 13.3.Configuring the External Memory Interface

  119
• 13.4.Port Configuration

  119
• 13.5.Multiplexed and Non-multiplexed Selection

  122
• 13.5.1.Multiplexed Configuration

  122
• 13.5.2.Non-multiplexed Configuration

  123
• 13.6.Memory Mode Selection

  123
• 13.6.1.Internal XRAM Only

  124
• 13.6.2.Split Mode without Bank Select

  124
• 13.6.3.Split Mode with Bank Select

  125
• 13.6.4.External Only

  125
• 13.7.Timing

  125
• 13.7.1.Non-multiplexed Mode

  127
• 13.7.2.Multiplexed Mode

  130
• 14. Oscillators

  135
• 14.1.Programmable Internal High-Frequency (H-F) Oscillator

  136
• 14.1.1.Internal H-F Oscillator Suspend Mode

  136
• 14.2.Programmable Internal Low-Frequency (L-F) Oscillator

  137
• 14.2.1.Calibrating the Internal L-F Oscillator

  137
• 14.3.External Oscillator Drive Circuit

  139
• 14.3.1.Clocking Timers Directly Through the External Oscillator

  139
• 14.3.2.External Crystal Example

  139
• 14.3.3.External RC Example

  140
• 14.3.4.External Capacitor Example

  140
• 14.4.4x Clock Multiplier

  142
• 14.5.System and USB Clock Selection

  143
• 14.5.1.System Clock Selection

  143
• 14.5.2.USB Clock Selection

  143
• 15. Port Input/Output

  147
• 15.1.Priority Crossbar Decoder

  149
• 15.2.Port I/O Initialization

  151
• 15.3.General Purpose Port I/O

  154
• 16. Universal Serial Bus Controller (USB0)

  163
• 16.1.Endpoint Addressing

  164
• 16.2.USB Transceiver

  164
• 16.3.USB Register Access

  166
• 16.4.USB Clock Configuration

  170
• 16.5.FIFO Management

  171
• 16.5.1.FIFO Split Mode

  171
• 16.5.2.FIFO Double Buffering

  172
• 16.5.3.FIFO Access

  172
• 16.6.Function Addressing

  173
• 16.7.Function Configuration and Control

  173
• 16.8.Interrupts

  176
• 16.9.The Serial Interface Engine

  180
• 16.10.Endpoint0

  180
• 16.10.1.Endpoint0 SETUP Transactions

  181
• 16.10.2.Endpoint0 IN Transactions

  181
• 16.10.3.Endpoint0 OUT Transactions

  182
• 16.11.Configuring Endpoints1-3

  184
• 16.12.Controlling Endpoints1-3 IN

  184
• 16.12.1.Endpoints1-3 IN Interrupt or Bulk Mode

  184
• 16.12.2.Endpoints1-3 IN Isochronous Mode

  185
• 16.13.Controlling Endpoints1-3 OUT

  187
• 16.13.1.Endpoints1-3 OUT Interrupt or Bulk Mode

  187
• 16.13.2.Endpoints1-3 OUT Isochronous Mode

  188
• 17. SMBus

  193
• 17.1.Supporting Documents

  194
• 17.2.SMBus Configuration

  194
• 17.3.SMBus Operation

  194
• 17.3.1.Arbitration

  195
• 17.3.2.Clock Low Extension

  196
• 17.3.3.SCL Low Timeout

  196
• 17.3.4.SCL High (SMBus Free) Timeout

  196
• 17.4.Using the SMBus

  196
• 17.4.1.SMBus Configuration Register

  198
• 17.4.2.SMB0CN Control Register

  201
• 17.4.3.Data Register

  204
• 17.5.SMBus Transfer Modes

  204
• 17.5.1.Master Transmitter Mode

  204
• 17.5.2.Master Receiver Mode

  206
• 17.5.3.Slave Receiver Mode

  207
• 17.5.4.Slave Transmitter Mode

  208
• 17.6.SMBus Status Decoding

  208
• 18. UART0

  211
• 18.1.Enhanced Baud Rate Generation

  212
• 18.2.Operational Modes

  212
• 18.2.1.8-Bit UART

  213
• 18.2.2.9-Bit UART

  214
• 18.3.Multiprocessor Communications

  214
• 19. UART1 (C8051F340/1/4/5 Only)

  219
• 19.1.Baud Rate Generator

  220
• 19.2.Data Format

  221
• 19.3.Configuration and Operation

  222
• 19.3.1.Data Transmission

  222
• 19.3.2.Data Reception

  222
• 19.3.3.Multiprocessor Communications

  223
• 20. Enhanced Serial Peripheral Interface (SPI0)

  229
• 20.1.Signal Descriptions

  230
• 20.1.1.Master Out, Slave In (MOSI)

  230
• 20.1.2.Master In, Slave Out (MISO)

  230
• 20.1.3.Serial Clock (SCK)

  230
• 20.1.4.Slave Select (NSS)

  230
• 20.2.SPI0 Master Mode Operation

  231
• 20.3.SPI0 Slave Mode Operation

  233
• 20.4.SPI0 Interrupt Sources

  233
• 20.5.Serial Clock Timing

  234
• 20.6.SPI Special Function Registers

  236
• 21. Timers

  243
• 21.1.Timer 0 and Timer 1

  243
• 21.1.1.Mode 0: 13-bit Counter/Timer

  243
• 21.1.2.Mode 1: 16-bit Counter/Timer

  244
• 21.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload

  245
• 21.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)

  246
• 21.2.Timer 2

  251
• 21.2.1.16-bit Timer with Auto-Reload

  251
• 21.2.2.8-bit Timers with Auto-Reload

  252
• 21.2.3.Timer 2 Capture Modes: USB Start-of-Frame or LFO Falling Edge

  253
• 21.3.Timer 3

  257
• 21.3.1.16-bit Timer with Auto-Reload

  257
• 21.3.2.8-bit Timers with Auto-Reload

  258
• 21.3.3.USB Start-of-Frame Capture

  259
• 22. Programmable Counter Array (PCA0)

  263
• 22.1.PCA Counter/Timer

  264
• 22.2.Capture/Compare Modules

  265
• 22.2.1.Edge-triggered Capture Mode

  266
• 22.2.2.Software Timer (Compare) Mode

  267
• 22.2.3.High Speed Output Mode

  268
• 22.2.4.Frequency Output Mode

  269
• 22.2.5.8-Bit Pulse Width Modulator Mode

  270
• 22.2.6.16-Bit Pulse Width Modulator Mode

  271
• 22.3.Watchdog Timer Mode

  272
• 22.3.1.Watchdog Timer Operation

  272
• 22.3.2.Watchdog Timer Usage

  273
• 22.4.Register Descriptions for PCA

  274
• 23. C2 Interface

  279
• 23.1.C2 Interface Registers

  279
• 23.2.C2 Pin Sharing

  281
• Contact Information

  282
• Table 1.1. Product Selection Guide

  18
• Figure 1.1. C8051F340/1/4/5 Block Diagram

  19
• Figure 1.2. C8051F342/3/6/7 Block Diagram

  20
• Figure 1.3. On-Chip Clock and Reset

  22
• Figure 1.4. On-Chip Memory Map for 64kB Devices (C8051F340/2/4/6)

  23
• Figure 1.5. USB Controller Block Diagram

  24
• Figure 1.6. Digital Crossbar Diagram

  26
• Figure 1.7. PCA Block Diagram

  27
• Figure 1.8. PCA Block Diagram

  27
• Figure 1.9. 10-Bit ADC Block Diagram

  28
• Figure 1.10. Comparator0 Block Diagram

  29
• Table 2.1. Absolute Maximum Ratings

  30
• Table 3.1. Global DC Electrical Characteristics

  31
• Table 3.2. Index to Electrical Characteristics Tables

  32
• Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7

  33
• Figure 4.1. TQFP-48 Pinout Diagram (Top View)

  36
• Table 4.2. TQFP-48 Package Dimensions

  37
• Figure 4.2. TQFP-48 Package Diagram

  37
• Figure 4.3. LQFP-32 Pinout Diagram (Top View)

  38
• Table 4.3. LQFP-32 Package Dimensions

  39
• Figure 4.4. LQFP-32 Package Diagram

  39
• Figure 5.1. ADC0 Functional Block Diagram

  41
• Figure 5.2. Temperature Sensor Transfer Function

  43
• Figure 5.4. 10-Bit ADC Track and Conversion Example Timing

  46
• Figure 5.5. ADC0 Equivalent Input Circuits

  47
• Figure 5.7. ADC Window Compare Example: Left-Justified Single-Ended Data

  54
• Figure 5.8. ADC Window Compare Example: Right-Justified Differential Data

  55
• Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data

  55
• Table 5.1. ADC0 Electrical Characteristics

  56
• Figure 6.1. Voltage Reference Functional Block Diagram

  57
• Table 6.1. Voltage Reference Electrical Characteristics

  58
• Figure 7.1. Comparator Functional Block Diagram

  60
• Figure 7.2. Comparator Hysteresis Plot

  61
• Table 7.1. Comparator Electrical Characteristics

  68
• Table 8.1. Voltage Regulator Electrical Specifications

  69
• Figure 8.1. REG0 Configuration: USB Bus-Powered

  70
• Figure 8.2. REG0 Configuration: USB Self-Powered

  70
• Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled

  71
• Figure 8.4. REG0 Configuration: No USB Connection

  71
• Figure 9.1. CIP-51 Block Diagram

  73
• Table 9.1. CIP-51 Instruction Set Summary

  75
• Figure 9.2. Memory Map

  79
• Table 9.2. Special Function Register (SFR) Memory Map

  81
• Table 9.3. Special Function Registers

  82
• Table 9.4. Interrupt Summary

  89
• Figure 11.1. Reset Sources

  101
• Figure 11.2. Power-On and VDD Monitor Reset Timing

  102
• Table 11.1. Reset Electrical Characteristics

  107
• Table 12.1. Flash Electrical Characteristics

  111
• Figure 12.1. Flash Program Memory Map and Security Byte

  112
• Figure 13.2. Multiplexed Configuration Example

  122
• Figure 13.3. Non-multiplexed Configuration Example

  123
• Figure 13.4. EMIF Operating Modes

  123
• Figure 13.5. Non-multiplexed 16-bit MOVX Timing

  127
• Figure 13.6. Non-multiplexed 8-bit MOVX without Bank Select Timing

  128
• Figure 13.7. Non-multiplexed 8-bit MOVX with Bank Select Timing

  129
• Figure 13.8. Multiplexed 16-bit MOVX Timing

  130
• Figure 13.9. Multiplexed 8-bit MOVX without Bank Select Timing

  131
• Figure 13.10. Multiplexed 8-bit MOVX with Bank Select Timing

  132
• Table 13.1. AC Parameters for External Memory Interface

  133
• Figure 14.1. Oscillator Diagram

  135
• Table 14.1. Oscillator Electrical Characteristics

  145
• Figure 15.1. Port I/O Functional Block Diagram (Port 0 through Port 3)

  147
• Figure 15.2. Port I/O Cell Block Diagram

  148
• Figure 15.3. Crossbar Priority Decoder with No Pins Skipped

  149
• Figure 15.4. Crossbar Priority Decoder with Crystal Pins Skipped

  150
• Table 15.1. Port I/O DC Electrical Characteristics

  162
• Figure 16.1. USB0 Block Diagram

  163
• Table 16.1. Endpoint Addressing Scheme

  164
• Figure 16.2. USB0 Register Access Scheme

  166
• Table 16.2. USB0 Controller Registers

  169
• Figure 16.3. USB FIFO Allocation

  171
• Table 16.3. FIFO Configurations

  172
• Table 16.4. USB Transceiver Electrical Characteristics

  191
• Figure 17.1. SMBus Block Diagram

  193
• Figure 17.2. Typical SMBus Configuration

  194
• Figure 17.3. SMBus Transaction

  195
• Table 17.1. SMBus Clock Source Selection

  198
• Figure 17.4. Typical SMBus SCL Generation

  199
• Table 17.2. Minimum SDA Setup and Hold Times

  199
• Table 17.3. Sources for Hardware Changes to SMB0CN

  203
• Figure 17.5. Typical Master Transmitter Sequence

  205
• Figure 17.6. Typical Master Receiver Sequence

  206
• Figure 17.7. Typical Slave Receiver Sequence

  207
• Figure 17.8. Typical Slave Transmitter Sequence

  208
• Table 17.4. SMBus Status Decoding

  209
• Figure 18.1. UART0 Block Diagram

  211
• Figure 18.2. UART0 Baud Rate Logic

  212
• Figure 18.3. UART Interconnect Diagram

  213
• Figure 18.4. 8-Bit UART Timing Diagram

  213
• Figure 18.5. 9-Bit UART Timing Diagram

  214
• Figure 18.6. UART Multi-Processor Mode Interconnect Diagram

  215
• Using The Internal Oscillator

  218
• Figure 19.1. UART1 Block Diagram

  219
• Table 19.1. Baud Rate Generator Settings for Standard Baud Rates

  220
• Figure 19.2. UART1 Timing Without Parity or Extra Bit

  221
• Figure 19.3. UART1 Timing With Parity

  221
• Figure 19.4. UART1 Timing With Extra Bit

  221
• Figure 19.5. Typical UART Interconnect Diagram

  222
• Figure 19.6. UART Multi-Processor Mode Interconnect Diagram

  223
• Figure 20.1. SPI Block Diagram

  229
• Figure 20.2. Multiple-Master Mode Connection Diagram

  232
• Figure 20.3. 3-Wire Single Master and Slave Mode Connection Diagram

  232
• Figure 20.5. Master Mode Data/Clock Timing

  234
• Figure 20.6. Slave Mode Data/Clock Timing (CKPHA = 0)

  235
• Figure 20.7. Slave Mode Data/Clock Timing (CKPHA = 1)

  235
• Figure 20.8. SPI Master Timing (CKPHA = 0)

  239
• Figure 20.9. SPI Master Timing (CKPHA = 1)

  239
• Figure 20.10. SPI Slave Timing (CKPHA = 0)

  240
• Figure 20.11. SPI Slave Timing (CKPHA = 1)

  240
• Table 20.1. SPI Slave Timing Parameters

  241
• Figure 21.1. T0 Mode 0 Block Diagram

  244
• Figure 21.2. T0 Mode 2 Block Diagram

  245
• Figure 21.3. T0 Mode 3 Block Diagram

  246
• Figure 21.4. Timer 2 16-Bit Mode Block Diagram

  251
• Figure 21.5. Timer 2 8-Bit Mode Block Diagram

  252
• Figure 21.6. Timer 2 Capture Mode (T2SPLIT = ‘0’)

  253
• Figure 21.7. Timer 2 Capture Mode (T2SPLIT = ‘1’)

  254
• Figure 21.8. Timer 3 16-Bit Mode Block Diagram

  257
• Figure 21.9. Timer 3 8-Bit Mode Block Diagram

  258
• Figure 21.10. Timer 3 Capture Mode (T3SPLIT = ‘0’)

  259
• Figure 21.11. Timer 3 Capture Mode (T3SPLIT = ‘1’)

  260
• Figure 22.1. PCA Block Diagram

  263
• Table 22.1. PCA Timebase Input Options

  264
• Figure 22.2. PCA Counter/Timer Block Diagram

  264
• Table 22.2. PCA0CPM Register Settings for PCA Capture/Compare Modules

  265
• Figure 22.3. PCA Interrupt Block Diagram

  265
• Figure 22.4. PCA Capture Mode Diagram

  266
• Figure 22.5. PCA Software Timer Mode Diagram

  267
• Figure 22.6. PCA High Speed Output Mode Diagram

  268
• Figure 22.7. PCA Frequency Output Mode

  269
• Figure 22.8. PCA 8-Bit PWM Mode Diagram

  270
• Figure 22.9. PCA 16-Bit PWM Mode

  271
• Figure 22.10. PCA Module 4 with Watchdog Timer Enabled

  272
• Table 22.3. Watchdog Timer Timeout Intervals1

  273
• Figure 23.1. Typical C2 Pin Sharing

  281
• BitRate =

  3
• DutyCycle =

  256
• DutyCycle =

  65536