Manuais de utilizador para SMSC flexpwr lan8710

índice analítico

• Chapter 1 Introduction

  9
  • 1.1 General Terms and Conventions

    9
  • 1.2 General Description

    9
    • Figure 1.1 LAN8710/LAN8710i System Block Diagram

      10
  • 1.3 Architectural Overview

    10
    • 1.3.1 Configuration

      10
      • Figure 1.2 LAN8710/LAN8710i Architectural Overview

        11
• Chapter 2 Pin Configuration

  12
  • 2.1 Package Pin-out Diagram and Signal Table

    12
    • Figure 2.1 LAN8710/LAN8710i 32-QFN Pin Assignments (TOP VIEW)

      12
    • Table 2.1 LAN8710/LAN8710i 32-PIN QFN Pinout

      13
• Chapter 3 Pin Description

  14
  • Table 3.1 Buffer Types

    14
  • 3.1 MAC Interface Signals

    14
    • Table 3.2 MII/RMII Signals 32-QFN

      14
  • 3.2 LED Signals

    16
    • Table 3.3 LED Signals 32-QFN

      16
  • 3.3 Management Signals

    17
    • Table 3.4 Management Signals 32-QFN

      17
  • 3.4 General Signals

    17
    • Table 3.5 General Signals 32-QFN

      17
  • 3.5 10/100 Line Interface Signals

    17
    • Table 3.6 10/100 Line Interface Signals 32-QFN

      17
  • 3.6 Analog Reference

    18
    • Table 3.7 Analog References 32-QFN

      18
  • 3.7 Power Signals

    18
    • Table 3.8 Power Signals 32-QFN

      18
• Chapter 4 Architecture Details

  19
  • 4.1 Top Level Functional Architecture

    19
    • Figure 4.1 100Base-TX Data Path

      19
  • 4.2 100Base-TX Transmit

    19
    • 4.2.1 100M Transmit Data Across the MII/RMII Interface

      19
    • 4.2.2 4B/5B Encoding

      20
      • Table 4.1 4B/5B Code Table

        20
    • 4.2.3 Scrambling

      21
    • 4.2.4 NRZI and MLT3 Encoding

      21
    • 4.2.5 100M Transmit Driver

      21
    • 4.2.6 100M Phase Lock Loop (PLL)

      22
      • Figure 4.2 Receive Data Path

        22
  • 4.3 100Base-TX Receive

    22
    • 4.3.1 100M Receive Input

      22
    • 4.3.2 Equalizer, Baseline Wander Correction and Clock and Data Recovery

      22
    • 4.3.3 NRZI and MLT-3 Decoding

      23
    • 4.3.4 Descrambling

      23
    • 4.3.5 Alignment

      23
    • 4.3.6 5B/4B Decoding

      23
    • 4.3.7 Receive Data Valid Signal

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      • Figure 4.3 Relationship Between Received Data and Specific MII Signals

        24
    • 4.3.8 Receiver Errors

      24
    • 4.3.9 100M Receive Data Across the MII/RMII Interface

      24
  • 4.4 10Base-T Transmit

    24
    • 4.4.1 10M Transmit Data Across the MII/RMII Interface

      24
    • 4.4.2 Manchester Encoding

      25
    • 4.4.3 10M Transmit Drivers

      25
  • 4.5 10Base-T Receive

    25
    • 4.5.1 10M Receive Input and Squelch

      25
    • 4.5.2 Manchester Decoding

      25
    • 4.5.3 10M Receive Data Across the MII/RMII Interface

      26
    • 4.5.4 Jabber Detection

      26
  • 4.6 MAC Interface

    26
    • 4.6.1 MII

      26
    • 4.6.2 RMII

      26
    • 4.6.3 MII vs. RMII Configuration

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      • Table 4.2 MII/RMII Signal Mapping

        28
  • 4.7 Auto-negotiation

    28
    • 4.7.1 Parallel Detection

      30
    • 4.7.2 Re-starting Auto-negotiation

      30
    • 4.7.3 Disabling Auto-negotiation

      30
    • 4.7.4 Half vs. Full Duplex

      30
  • 4.8 HP Auto-MDIX Support

    30
    • Figure 4.4 Direct Cable Connection vs. Cross-over Cable Connection

      31
  • 4.9 Internal +1.2V Regulator Disable

    31
    • 4.9.1 Disable the Internal +1.2V Regulator

      31
    • 4.9.2 Enable the Internal +1.2V Regulator

      31
  • 4.10 nINTSEL Strapping and LED Polarity Selection

    32
    • Figure 4.5 nINTSEL Strapping on LED2

      32
  • 4.11 REGOFF and LED Polarity Selection

    32
    • Figure 4.6 REGOFF Configuration on LED1

      33
  • 4.12 PHY Address Strapping

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  • 4.13 Variable Voltage I/O

    33
  • 4.14 Transceiver Management Control

    33
    • 4.14.1 Serial Management Interface (SMI)

      33
      • Figure 4.7 MDIO Timing and Frame Structure - READ Cycle

        34
      • Figure 4.8 MDIO Timing and Frame Structure - WRITE Cycle

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• Chapter 5 SMI Register Mapping

  35
  • Table 5.1 Control Register: Register 0 (Basic)

    35
  • Table 5.2 Status Register: Register 1 (Basic)

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  • Table 5.3 PHY ID 1 Register: Register 2 (Extended)

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  • Table 5.4 PHY ID 2 Register: Register 3 (Extended)

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  • Table 5.5 Auto-Negotiation Advertisement: Register 4 (Extended)

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  • Table 5.6 Auto-Negotiation Link Partner Base Page Ability Register: Register 5 (Extended)

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  • Table 5.7 Auto-Negotiation Expansion Register: Register 6 (Extended)

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  • Table 5.8 Register 15 (Extended)

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  • Table 5.9 Silicon Revision Register 16: Vendor-Specific

    36
  • Table 5.10 Mode Control/ Status Register 17: Vendor-Specific

    37
  • Table 5.11 Special Modes Register 18: Vendor-Specific

    37
  • Table 5.12 Register 24: Vendor-Specific

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  • Table 5.13 Register 25: Vendor-Specific

    37
  • Table 5.14 Symbol Error Counter Register 26: Vendor-Specific

    37
  • Table 5.15 Special Control/Status Indications Register 27: Vendor-Specific

    38
  • Table 5.16 Special Internal Testability Control Register 28: Vendor-Specific

    38
  • Table 5.17 Interrupt Source Flags Register 29: Vendor-Specific

    38
  • Table 5.18 Interrupt Mask Register 30: Vendor-Specific

    38
  • Table 5.19 PHY Special Control/Status Register 31: Vendor-Specific

    38
  • Table 5.20 SMI Register Mapping

    39
  • 5.1 SMI Register Format

    39
    • Table 5.21 Register 0 - Basic Control

      40
    • Table 5.22 Register 1 - Basic Status

      40
    • Table 5.23 Register 2 - PHY Identifier 1

      41
    • Table 5.24 Register 3 - PHY Identifier 2

      41
    • Table 5.25 Register 4 - Auto Negotiation Advertisement

      41
    • Table 5.26 Register 5 - Auto Negotiation Link Partner Ability

      42
    • Table 5.27 Register 6 - Auto Negotiation Expansion

      43
    • Table 5.28 Register 16 - Silicon Revision

      43
    • Table 5.29 Register 17 - Mode Control/Status

      43
    • Table 5.30 Register 18 - Special Modes

      44
    • Table 5.31 Register 26 - Symbol Error Counter

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    • Table 5.32 Register 27 - Special Control/Status Indications

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    • Table 5.33 Register 28 - Special Internal Testability Controls

      45
    • Table 5.34 Register 29 - Interrupt Source Flags

      45
    • Table 5.35 Register 30 - Interrupt Mask

      46
    • Table 5.36 Register 31 - PHY Special Control/Status

      46
  • 5.2 Interrupt Management

    47
    • 5.2.1 Primary Interrupt System

      47
      • Table 5.37 Interrupt Management Table

        47
    • 5.2.2 Alternate Interrupt System

      48
      • Table 5.38 Alternative Interrupt System Management Table

        48
  • 5.3 Miscellaneous Functions

    48
    • 5.3.1 Carrier Sense

      48
    • 5.3.2 Collision Detect

      49
    • 5.3.3 Isolate Mode

      49
    • 5.3.4 Link Integrity Test

      49
    • 5.3.5 Power-Down modes

      49
    • 5.3.6 Reset

      50
    • 5.3.7 LED Description

      50
    • 5.3.8 Loopback Operation

      50
      • Figure 5.1 Near-end Loopback Block Diagram

        51
      • Figure 5.2 Far Loopback Block Diagram

        51
      • Figure 5.3 Connector Loopback Block Diagram

        52
    • 5.3.9 Configuration Signals

      52
      • Table 5.39 Pin Names for Address Bits

        52
      • Table 5.40 MODE[2:0] Bus

        53
      • Table 5.41 Pin Names for Mode Bits

        53
• Chapter 6 AC Electrical Characteristics

  55
  • 6.1 Serial Management Interface (SMI) Timing

    55
    • Figure 6.1 SMI Timing Diagram

      55
    • Table 6.1 SMI Timing Values

      55
  • 6.2 MII 10/100Base-TX/RX Timings

    56
    • 6.2.1 MII 100Base-T TX/RX Timings

      56
      • Figure 6.2 100M MII Receive Timing Diagram

        56
      • Table 6.2 100M MII Receive Timing Values

        56
      • Figure 6.3 100M MII Transmit Timing Diagram

        57
      • Table 6.3 100M MII Transmit Timing Values

        57
    • 6.2.2 MII 10Base-T TX/RX Timings

      58
      • Figure 6.4 10M MII Receive Timing Diagram

        58
      • Table 6.4 10M MII Receive Timing Values

        58
      • Figure 6.5 10M MII Transmit Timing Diagrams

        59
      • Table 6.5 10M MII Transmit Timing Values

        59
  • 6.3 RMII 10/100Base-TX/RX Timings (50MHz REF_CLK IN)

    60
    • 6.3.1 RMII 100Base-T TX/RX Timings (50MHz REF_CLK IN)

      60
      • Figure 6.6 100M RMII Receive Timing Diagram (50MHz REF_CLK IN)

        60
      • Table 6.6 100M RMII Receive Timing Values (50MHz REF_CLK IN)

        60
      • Figure 6.7 100M RMII Transmit Timing Diagram (50MHz REF_CLK IN)

        61
      • Table 6.7 100M RMII Transmit Timing Values (50MHz REF_CLK IN)

        61
    • 6.3.2 RMII 10Base-T TX/RX Timings (50MHz REF_CLK IN)

      62
      • Figure 6.8 10M RMII Receive Timing Diagram (50MHz REF_CLK IN)

        62
      • Table 6.8 10M RMII Receive Timing Values (50MHz REF_CLK IN)

        62
      • Figure 6.9 10M RMII Transmit Timing Diagram (50MHz REF_CLK IN)

        63
      • Table 6.9 10M RMII Transmit Timing Values (50MHz REF_CLK IN)

        63
  • 6.4 RMII CLKIN Requirements

    64
    • Table 6.10 RMII CLKIN (REF_CLK) Timing Values

      64
  • 6.5 Reset Timing

    64
    • Figure 6.10 Reset Timing Diagram

      64
    • Table 6.11 Reset Timing Values

      64
  • 6.6 Clock Circuit

    65
    • Table 6.12 LAN8710/LAN8710i Crystal Specifications

      65
• Chapter 7 DC Electrical Characteristics

  66
  • 7.1 DC Characteristics

    66
    • 7.1.1 Maximum Guaranteed Ratings

      66
      • Table 7.1 Maximum Conditions

        66
      • Table 7.2 ESD and LATCH-UP Performance

        66
    • 7.1.2 Operating Conditions

      67
      • Table 7.3 Recommended Operating Conditions

        67
    • 7.1.3 Power Consumption

      68
      • Table 7.4 Power Consumption Device Only

        68
    • 7.1.4 DC Characteristics - Input and Output Buffers

      69
      • Table 7.5 MII Bus Interface Signals

        69
      • Table 7.6 LAN Interface Signals

        70
      • Table 7.7 LED Signals

        70
      • Table 7.8 Configuration Inputs

        70
      • Table 7.9 General Signals

        70
      • Table 7.10 Internal Pull-Up / Pull-Down Configurations

        71
      • Table 7.11 100Base-TX Transceiver Characteristics

        71
      • Table 7.12 10BASE-T Transceiver Characteristics

        72
• Chapter 8 Application Notes

  73
  • 8.1 Application Diagram

    73
    • 8.1.1 MII Diagram

      73
      • Figure 8.1 Simplified Application Diagram

        73
    • 8.1.2 Power Supply Diagram

      74
      • Figure 8.2 High-Level System Diagram for Power

        74
    • 8.1.3 Twisted-Pair Interface Diagram

      74
      • Figure 8.4 Copper Interface Diagram

        74
  • 8.2 Magnetics Selection

    75
• Chapter 9 Package Outline

  76
  • Figure 9.1 LAN8710/LAN8710i-EZK 32 Pin QFN Package Outline, 5 x 5 x 0.9 mm Body (Lead-Free)

    76
  • Table 9.1 32 Terminal QFN Package Parameters

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  • Figure 9.1 QFN, 5x5 Taping Dimensions and Part Orientation

    77
  • Figure 9.2 Reel Dimensions for 12mm Carrier Tape

    78
  • Figure 9.3 Tape Length and Part Quantity

    79