Manuais de utilizador para Texas Instruments TMS320C6722

índice analítico

• 1 TMS320C6727, TMS320C6726, TMS320C6722 DSPs

  1
  • 1.1 Features

    1
  • 1.2 Description

    2
  • 1.2.1 Device Compatibility

    4
  • 1.3 Functional Block Diagram

    5
• Table of Contents

  6
• 2 Device Overview

  7
  • 2.1 Device Characteristics

    7
  • 2.2 Enhanced C67x+ CPU

    8
  • 2.3 CPU Interrupt Assignments

    9
  • 2.4 Internal Program/Data ROM and RAM

    10
  • 2.5 Program Cache

    11
  • 2.6 High-Performance Crossbar Switch

    12
  • 2.7 Memory Map Summary

    15
  • 2.8 Boot Modes

    16
  • 2.9 Pin Assignments

    19
    • 2.9.1 Pin Maps

      19
    • 2.9.2 Terminal Functions

      21
  • 2.10 Development

    26
    • 2.10.1 Development Support

      26
    • 2.10.2 Device Support

      26
• 3 Device Configurations

  30
  • 3.1 Device Configuration Registers

    30
  • 3.2 Peripheral Pin Multiplexing Options

    30
  • 3.3 Peripheral Pin Multiplexing Control

    31
• 4 Peripheral and Electrical Specifications

  33
  • 4.1 Electrical Specifications

    33
  • 4.2 Absolute Maximum Ratings

    33
  • 4.3 Recommended Operating Conditions

    33
  • 4.4 Electrical Characteristics

    34
  • 4.5 Parameter Information

    35
    • 4.5.1 Parameter Information Device-Specific Information

      35
  • 4.6 Timing Parameter Symbology

    36
  • 4.7 Power Supplies

    37
    • 4.7.1 Power-Supply Sequencing

      37
    • 4.7.2 Power-Supply Decoupling

      37
  • 4.8 Reset

    38
    • 4.8.1 Reset Electrical Data/Timing

      38
  • 4.9 Dual Data Movement Accelerator (dMAX)

    39
    • 4.9.1 dMAX Device-Specific Information

      39
    • 4.9.2 dMAX Peripheral Registers Description(s)

      43
  • 4.10 External Interrupts

    44
  • 4.11 External Memory Interface (EMIF)

    45
    • 4.11.1 EMIF Device-Specific Information

      45
    • 4.11.2 EMIF Peripheral Registers Description(s)

      48
    • 4.11.3 EMIF Electrical Data/Timing

      49
  • 4.12 Universal Host-Port Interface (UHPI) [C6727 Only]

    55
    • 4.12.1 UHPI Device-Specific Information

      55
    • 4.12.2 UHPI Peripheral Registers Description(s)

      59
    • 4.12.3 UHPI Electrical Data/Timing

      62
  • 4.13  Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)

    68
    • 4.13.1 McASP Peripheral Registers Description(s)

      70
    • 4.13.2 McASP Electrical Data/Timing

      76
  • 4.14 Serial Peripheral Interface Ports (SPI0, SPI1)

    80
    • 4.14.1 SPI Device-Specific Information

      80
    • 4.14.2 SPI Peripheral Registers Description(s)

      82
    • 4.14.3 SPI Electrical Data/Timing

      83
  • 4.15 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)

    93
    • 4.15.1 I2C Device-Specific Information

      93
    • 4.15.2 I2C Peripheral Registers Description(s)

      94
    • 4.15.3 I2C Electrical Data/Timing

      95
  • 4.16 Real-Time Interrupt (RTI) Timer With Digital Watchdog

    97
    • 4.16.1 RTI/Digital Watchdog Device-Specific Information

      97
    • 4.16.2 RTI/Digital Watchdog Registers Description(s)

      98
  • 4.17 External Clock Input From Oscillator or CLKIN Pin

    100
    • 4.17.1 Clock Electrical Data/Timing

      101
  • 4.18 Phase-Locked Loop (PLL)

    102
    • 4.18.1 PLL Device-Specific Information

      102
    • 4.18.2 PLL Registers Description(s)

      104
• 5 Application Example

  105
• 6 Revision History

  106
• 7 Mechanical Data

  107
  • 7.1 Package Thermal Resistance Characteristics

    107
  • 7.2 Supplementary Information About the 144-Pin RFP PowerPAD Package

    108
    • 7.2.1 Standoff Height

      108
    • 7.2.2 PowerPAD PCB Footprint

      109
  • 7.3 Packaging Information

    109