Справочник Пользователя для Hitachi H8/3692
Rev. 1.0, 07/01, page 231 of 372
Bit
Bit Name
Initial Value R/W
Description
5
RDRF
0
R/W
Receive Data Register Full
[Setting condition]
•
When a receive data is transferred from ICDRS to
ICDRR
[Clearing conditions]
•
When 0 is written in RDRF after reading RDRF = 1
•
When ICDRR is read with an instruction
4
NACKF
0
R/W
No Acknowledge Detection Flag
[Setting condition]
•
When no acknowledge is detected from the receive
device in transmission while the ACKE bit in ICIER is 1
[Clearing condition]
•
When 0 is written in NACKF after reading NACKF = 1
3
STOP
0
R/W
Stop Condition Detection Flag
[Setting condition]
•
When a stop condition is detected after frame transfer
[Clearing condition]
•
When 0 is written in STOP after reading STOP = 1
2
AL/OVE
0
R/W
Arbitration Lost Flag/Overrun Error Flag
This flag indicates that arbitration was lost in master mode
with the I
with the I
2
C bus format and that the final bit has been
received while RDRF = 1 with the clocked synchronous
format.
format.
When two or more master devices attempt to seize the bus
at nearly the same time, if the I
at nearly the same time, if the I
2
C bus interface detects data
differing from the data it sent, it sets AL to 1 to indicate that
the bus has been taken by another master.
the bus has been taken by another master.
[Setting conditions]
•
If the internal SDA and SDA pin disagree at the rise of
SCL in master transmit mode
•
When the SDA pin outputs high in master mode while a
start condition is detected
•
When the final bit is received with the clocked
synchronous format while RDRF = 1
[Clearing condition]
•
When 0 is written in AL/OVE after reading AL/OVE=1