Справочник Пользователя для Mitsubishi Electronics MELSEC -Q/L

2  INSTRUCTION TABLES
2.3  Sequence Instructions

*1 The number of steps may vary depending on the device being used.

*2 The number of steps may differ, depending on the device or CPU module to be used.

*3 For the High-speed Universal model QCPU, the number of basic steps is two.

*1 The number of steps may differ, depending on CPU modules.

Internal device, file register (R0 to R32767)

1

Direct access input (DX)

2

Devices other than above

3

Basic model QCPU
High Performance model QCPU
Process CPU
Redundant CPU

• Internal device, file register (R0 to R32767)
• Direct access input (DX)

1

Devices other than above

3

Universal model QCPU
LCPU

Internal device, file register (R0 to R32767)

Number of basic steps

• Serial number access format file register (ZR), Extended data register 

(D), Extended link register (W), Multiple CPU shared device 
(U3En\G10000)

• Direct access input (DX)

Number of basic steps +1

Devices other than above

Number of basic steps +2

Connection

ANB

• AND between logical blocks 

(Series connection between 
logical blocks)

1



ORB

• OR between logical blocks 

(Series connection between 
logical blocks)

MPS

• Memory storage of operation 

results

1



MRD

• Read of operation results 

stored with MPS instruction

MPP

• Read and reset of operation 

results stored with MPS 
instruction

INV

• Inversion of operation result

1



MEP

• Conversion of operation result 

to leading edge pulse

1



MEF

• Conversion of operation result 

to trailing edge pulse

EGP

• Conversion of operation result 

to leading edge pulse (Stored 
at Vn)

1



EGF

• Conversion of operation result 

to trailing edge pulse (Stored at 
Vn)

High Performance model QCPU
Process CPU
Redundant CPU
Universal model QCPU
LCPU

1

Basic model QCPU

2

ANB

ORB

MPS

MRD

MPP

Vn

Vn