Справочник Пользователя для Mitsubishi Electronics MELSEC -Q/L

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7 APPLICATION INSTRUCTIONS
7.3 Shift Instructions

n-bit shift to right of n-bit data, n-bit shift to left of n-bit data

SFTBR(P), SFTBL(P)

*1 T, ST, and C devices are not available.

Processing details

■SFTBR(P)

• This instruction shifts the n1 bits data in the devices starting from the device specified by (D) to the right by n2 bits.
n1=10, n2=4

• n1 and n2 are specified under the condition that n1 is larger than n2. If the value of n2 is equal to or larger than the value of

n1, the remainder of n2 / n1 (n2 divided by n1) is used for a shift. However, if the remainder of n2 / n1 is 0, the instruction
will be not processed.

• This instruction specifies n1 ranged from 1 to 64.
• Bits starting from the highest bit to n2th bit are filled with 0s. If the value of n2 is larger than the value of n1, the remainder

of n2 / n1 will be 0.

• If the value specified by n1 or n2 is 0, the instruction will be not processed.

• QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later
• Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported

(D):   Head number of the devices to be shifted (bits)
n1:   Number of bits to be shifted (BIN 16 bits)
n2:   Number of shifts (BIN 16 bits)

Setting
data

Internal device

R, ZR

J\

U\G

Constant
K, H

Others

Bit

Word

Bit

Word

(D)













Basic

High

performance

rocess

Redundant

Universal

LCPU

Ver.

Command

SFTBR, SFTBL

SFTBRP, SFTBLP

indicates an inst

ruction symbol of SFTBR/SFTBL.

Filled

with 0s

rry flag

(SM700)