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APPENDICES 
Appendix 1  Operation Processing Time
Operation processing time of Basic model QCPU
The processing time for the individual instructions are shown in the table on the following pages.
Operation processing times can vary substantially depending on the nature of the sources and destinations of the instructions, 
and the values contained in the following tables should therefore be taken as a set of general guidelines to processing time 
rather than as being strictly accurate.
When using the file resister (ZR), module access device (Un\G, U3En\G0 to G511), or link direct device 
(Jn\), add the processing time shown in Page 899 Table of the time to be added when file register, module 
access device or link direct device is used t
o that of each instruction.
Processing time
Sequence instructions
Instruction
Condition (device)
Processing time (
s)
Q00JCPU
Q00CPU
Q01CPU
LD
LDI
AND
ANI
OR
ORI
X0
0.20
0.16
0.10
D0.0
0.30
0.24
0.15
LDP
LDF
ANDP
ANDF
ORP
ORF
X0
0.30
0.24
0.15
D0.0
ANB
ORB
MPS
MRD
MPP
0.20
0.16
0.10
INV
When not executed
0.20
0.16
0.10
When executed
MEP
MEF
When not executed
0.30
0.24
0.15
When executed
EGP
When 
not 
executed
(OFF
OFF)
(ON
ON)
0.20
0.16
0.10
When 
executed
(OFF
ON)
(ON
OFF)
EGF
When 
not 
executed
(OFF
OFF)
(ON
ON)
17
9.5
9.4
When 
executed
(OFF
ON)
(ON
OFF)
18
14
14