Справочник Пользователя для Mitsubishi Electronics 00UCPU

118

This section describes data communications among CPU modules in a multiple CPU system using the CPU shared 
memory.

The CPU shared memory is a data storage area in a CPU module and used to read/write data among CPU 
modules in a multiple CPU system.
The CPU shared memory consists of the areas listed below.

Use of the multiple CPU high speed transmission area enables high-speed transmission by reducing the increase in scan 
time. Some conditions apply to using the area.

 • Data communications by auto refresh: 

 • Data communications by programs: 

Host CPU operation information area

An area used to store error information and LED status of the CPU 
module

System area

An area used by the operating system of the CPU module

–

Auto refresh area

An area used to communicate data by auto refresh.
This area starts from the next address of the last address in the 
system area.

User setting area

An area used to communicate data by a program.
This area is assigned to the later addresses of those used for the 
auto refresh area. If auto refresh is not performed, the area starts 
from the next address of the last address in the system area.

Multiple CPU high speed 
transmission area

An area to communicate data with other CPU modules in the 
multiple CPU system using Universal model QCPUs (except the 
Q00UCPU, Q01UCPU, and Q02UCPU)

User setting area

An area used to communicate data by a program.
This area is assigned to the address 10000

H

 and later of the CPU 

shared memory.

Auto refresh area

An area used to communicate data by auto refresh