Справочник Пользователя для Intel Server Board S5500HCV S5500HCVR

timing, technology and size, CPU 2 memory channels D, E, and F can have a different 
match of the parameters, channel RAS still functions. 

13. The Minimal memory population possible is {DIMM_A1}. In this configuration, the system 

operates in the Independent Channel Mode. Mirrored Channel Mode is not possible. 

14. The minimal population upgrade recommended for enabling CPU 2 socket is {DIMM_A1 

and DIMM_D1}. This configuration supports only the Independent Channel mode. 

15. In the Mirrored Channel mode, memory population on Channels A and B should be 

identical, including across adjacent slots on the channels, memory population on 
Channels D and E should be identical, including across adjacent slots on the channels. 
The DIMMs on successive slots are not required to be identical and can have different 
sizes and/or timings, but the overall channel timing reduces according to the slowest 
DIMM. If Channels A and B are not identical, or Channels D and E are not identical, the 
BIOS selects default Independent Channel Mode.  

16. If Channel C or F is not empty, the BIOS disables the Mirrored Channel Mode. 
17. When only CPU1 socket is populated, minimal population upgrade for Mirrored Channel 

Mode is {DIMM_A1 and DIMM_B1}. DIMM_A1 and DIMM_B1 must be identical, or will 
fall back to Independent Channel Mode. 

18. When both CPU sockets are populated, minimal population upgrade for the Mirrored 

Channel Mode is {DIMM_A1, DIMM_B1, DIMM_D1, DIMM_E1}. DIMM_A1 and 
DIMM_B1 as a pair must be identical, and so must DIMM_D1 and DIMM_E1 as a pair. 
The DIMMs on different CPU sockets need not be identical in size and/or sizing, 
although overall channel timing reduces according to the slowest DIMM. 

 

The following sections describe the memory configurations supported and validated on the 
Intel

®

 Server Boards S5520HC and S5500HCV.  

The following categories of memory configurations are supported: 



 

 – These configurations were verified by Intel to work but only limited 

validation was performed. Not all possible DDR3 DIMM configurations were validated 
due to the large number of possible configuration combinations. Supported 
configurations are highlighted in light gray in Tables 5 and 6. 



 

 – These configurations have received broad validation by Intel. Intel can 

provide customers with information on specific configurations that were validated. 
Validated configurations are highlighted in dark gray in Tables 5 and 6. 



 

All populated DIMMs are identical. 

 
The following is a description of the columns in Tables 5 and 6: 



 

X – Indicates the DIMM is populated. 



 

M – Indicates whether the configuration supports the Mirrored Channel mode of 
operation. It is one of the following: Y indicating Yes; N indicating No.