Справочник Пользователя для Intel 315889-002
315889-002
49
Z(f) Constant Output Impedance Design
A
Z(f) Constant Output
Impedance Design
A.1
Introduction - PROPOSED
The VRM/EVRD performance specification is based on the concept of output impedance,
commonly known as the load line. The impedance is determined by the Pulse Width
Modulator (PWM) controller’s Adaptive Voltage Positioning (AVP), up to the loop
bandwidth of the regulator and the impedance of the output filter and socket beyond
the loop bandwidth.
commonly known as the load line. The impedance is determined by the Pulse Width
Modulator (PWM) controller’s Adaptive Voltage Positioning (AVP), up to the loop
bandwidth of the regulator and the impedance of the output filter and socket beyond
the loop bandwidth.
Figure A-1. Typical Intel
®
Microprocessor Voltage Regulator Validation Setup
VTT
PWM
Vin
Z
PCB1
Z
PCB2
Z
Pskt
Z
Bulk
Z
HF1
Z
HF2
V
FB